config.ini (9213:5cab5448909c) config.ini (9276:a5ede748a1d9)
1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8

--- 118 unchanged lines hidden (view full) ---

127[system.cpu.dcache]
128type=BaseCache
129addr_ranges=0:18446744073709551615
130assoc=2
131block_size=64
132clock=1
133forward_snoops=true
134hash_delay=1
1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8

--- 118 unchanged lines hidden (view full) ---

127[system.cpu.dcache]
128type=BaseCache
129addr_ranges=0:18446744073709551615
130assoc=2
131block_size=64
132clock=1
133forward_snoops=true
134hash_delay=1
135hit_latency=1000
135is_top_level=true
136is_top_level=true
136latency=1000
137max_miss_count=0
138mshrs=10
139prefetch_on_access=false
140prefetcher=Null
141prioritizeRequests=false
142repl=Null
137max_miss_count=0
138mshrs=10
139prefetch_on_access=false
140prefetcher=Null
141prioritizeRequests=false
142repl=Null
143response_latency=1000
143size=262144
144subblock_size=0
145system=system
146tgts_per_mshr=20
147trace_addr=0
148two_queue=false
149write_buffers=8
150cpu_side=system.cpu.dcache_port

--- 277 unchanged lines hidden (view full) ---

428[system.cpu.icache]
429type=BaseCache
430addr_ranges=0:18446744073709551615
431assoc=2
432block_size=64
433clock=1
434forward_snoops=true
435hash_delay=1
144size=262144
145subblock_size=0
146system=system
147tgts_per_mshr=20
148trace_addr=0
149two_queue=false
150write_buffers=8
151cpu_side=system.cpu.dcache_port

--- 277 unchanged lines hidden (view full) ---

429[system.cpu.icache]
430type=BaseCache
431addr_ranges=0:18446744073709551615
432assoc=2
433block_size=64
434clock=1
435forward_snoops=true
436hash_delay=1
437hit_latency=1000
436is_top_level=true
438is_top_level=true
437latency=1000
438max_miss_count=0
439mshrs=10
440prefetch_on_access=false
441prefetcher=Null
442prioritizeRequests=false
443repl=Null
439max_miss_count=0
440mshrs=10
441prefetch_on_access=false
442prefetcher=Null
443prioritizeRequests=false
444repl=Null
445response_latency=1000
444size=131072
445subblock_size=0
446system=system
447tgts_per_mshr=20
448trace_addr=0
449two_queue=false
450write_buffers=8
451cpu_side=system.cpu.icache_port

--- 25 unchanged lines hidden (view full) ---

477[system.cpu.l2cache]
478type=BaseCache
479addr_ranges=0:18446744073709551615
480assoc=2
481block_size=64
482clock=1
483forward_snoops=true
484hash_delay=1
446size=131072
447subblock_size=0
448system=system
449tgts_per_mshr=20
450trace_addr=0
451two_queue=false
452write_buffers=8
453cpu_side=system.cpu.icache_port

--- 25 unchanged lines hidden (view full) ---

479[system.cpu.l2cache]
480type=BaseCache
481addr_ranges=0:18446744073709551615
482assoc=2
483block_size=64
484clock=1
485forward_snoops=true
486hash_delay=1
487hit_latency=1000
485is_top_level=false
488is_top_level=false
486latency=1000
487max_miss_count=0
488mshrs=10
489prefetch_on_access=false
490prefetcher=Null
491prioritizeRequests=false
492repl=Null
489max_miss_count=0
490mshrs=10
491prefetch_on_access=false
492prefetcher=Null
493prioritizeRequests=false
494repl=Null
495response_latency=1000
493size=2097152
494subblock_size=0
495system=system
496tgts_per_mshr=5
497trace_addr=0
498two_queue=false
499write_buffers=8
500cpu_side=system.cpu.toL2Bus.master[0]

--- 38 unchanged lines hidden (view full) ---

539header_cycles=1
540use_default_range=false
541width=8
542master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
543slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
544
545[system.physmem]
546type=SimpleMemory
496size=2097152
497subblock_size=0
498system=system
499tgts_per_mshr=5
500trace_addr=0
501two_queue=false
502write_buffers=8
503cpu_side=system.cpu.toL2Bus.master[0]

--- 38 unchanged lines hidden (view full) ---

542header_cycles=1
543use_default_range=false
544width=8
545master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
546slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
547
548[system.physmem]
549type=SimpleMemory
550bandwidth=73.000000
547clock=1
548conf_table_reported=false
551clock=1
552conf_table_reported=false
549file=
550in_addr_map=true
551latency=30000
552latency_var=0
553null=false
554range=0:134217727
555zero=false
556port=system.membus.master[0]
557
553in_addr_map=true
554latency=30000
555latency_var=0
556null=false
557range=0:134217727
558zero=false
559port=system.membus.master[0]
560