config.ini (9039:9a22621c741c) | config.ini (9096:8971a998190a) |
---|---|
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 486 unchanged lines hidden (view full) --- 495mem_side=system.membus.slave[1] 496 497[system.cpu.toL2Bus] 498type=CoherentBus 499block_size=64 500clock=1000 501header_cycles=1 502use_default_range=false | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 486 unchanged lines hidden (view full) --- 495mem_side=system.membus.slave[1] 496 497[system.cpu.toL2Bus] 498type=CoherentBus 499block_size=64 500clock=1000 501header_cycles=1 502use_default_range=false |
503width=64 | 503width=8 |
504master=system.cpu.l2cache.cpu_side 505slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 506 507[system.cpu.tracer] 508type=ExeTracer 509 510[system.cpu.workload] 511type=LiveProcess --- 15 unchanged lines hidden (view full) --- 527uid=100 528 529[system.membus] 530type=CoherentBus 531block_size=64 532clock=1000 533header_cycles=1 534use_default_range=false | 504master=system.cpu.l2cache.cpu_side 505slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 506 507[system.cpu.tracer] 508type=ExeTracer 509 510[system.cpu.workload] 511type=LiveProcess --- 15 unchanged lines hidden (view full) --- 527uid=100 528 529[system.membus] 530type=CoherentBus 531block_size=64 532clock=1000 533header_cycles=1 534use_default_range=false |
535width=64 | 535width=8 |
536master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave 537slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 538 539[system.physmem] 540type=SimpleMemory 541conf_table_reported=false 542file= 543in_addr_map=true 544latency=30000 545latency_var=0 546null=false 547range=0:134217727 548zero=false 549port=system.membus.master[0] 550 | 536master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave 537slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 538 539[system.physmem] 540type=SimpleMemory 541conf_table_reported=false 542file= 543in_addr_map=true 544latency=30000 545latency_var=0 546null=false 547range=0:134217727 548zero=false 549port=system.membus.master[0] 550 |