| config.ini (11680:b4d943429dc6) | config.ini (11731:c473ca7cc650) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 169 unchanged lines hidden (view full) --- 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 169 unchanged lines hidden (view full) --- 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl |
| 186data_latency=2 |
|
| 186default_p_state=UNDEFINED 187demand_mshr_reserve=1 188eventq_index=0 | 187default_p_state=UNDEFINED 188demand_mshr_reserve=1 189eventq_index=0 |
| 189hit_latency=2 | |
| 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system | 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system |
| 203tag_latency=2 |
|
| 203tags=system.cpu.dcache.tags 204tgts_per_mshr=20 205write_buffers=8 206writeback_clean=false 207cpu_side=system.cpu.dcache_port 208mem_side=system.cpu.toL2Bus.slave[1] 209 210[system.cpu.dcache.tags] 211type=LRU 212assoc=2 213block_size=64 214clk_domain=system.cpu_clk_domain | 204tags=system.cpu.dcache.tags 205tgts_per_mshr=20 206write_buffers=8 207writeback_clean=false 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dcache.tags] 212type=LRU 213assoc=2 214block_size=64 215clk_domain=system.cpu_clk_domain |
| 216data_latency=2 |
|
| 215default_p_state=UNDEFINED 216eventq_index=0 | 217default_p_state=UNDEFINED 218eventq_index=0 |
| 217hit_latency=2 | |
| 218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 221power_model=Null 222sequential_access=false 223size=262144 | 219p_state_clk_gate_bins=20 220p_state_clk_gate_max=1000000000000 221p_state_clk_gate_min=1000 222power_model=Null 223sequential_access=false 224size=262144 |
| 225tag_latency=2 |
|
| 224 225[system.cpu.dtb] 226type=X86TLB 227children=walker 228eventq_index=0 229size=64 230walker=system.cpu.dtb.walker 231 --- 76 unchanged lines hidden (view full) --- 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc | 226 227[system.cpu.dtb] 228type=X86TLB 229children=walker 230eventq_index=0 231size=64 232walker=system.cpu.dtb.walker 233 --- 76 unchanged lines hidden (view full) --- 310type=OpDesc 311eventq_index=0 312opClass=FloatCvt 313opLat=2 314pipelined=true 315 316[system.cpu.fuPool.FUList3] 317type=FUDesc |
| 316children=opList0 opList1 opList2 | 318children=opList0 opList1 opList2 opList3 opList4 |
| 317count=2 318eventq_index=0 | 319count=2 320eventq_index=0 |
| 319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 | 321opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 |
| 320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 | 322 323[system.cpu.fuPool.FUList3.opList0] 324type=OpDesc 325eventq_index=0 326opClass=FloatMult 327opLat=4 328pipelined=true 329 330[system.cpu.fuPool.FUList3.opList1] 331type=OpDesc 332eventq_index=0 |
| 333opClass=FloatMultAcc 334opLat=5 335pipelined=true 336 337[system.cpu.fuPool.FUList3.opList2] 338type=OpDesc 339eventq_index=0 340opClass=FloatMisc 341opLat=3 342pipelined=true 343 344[system.cpu.fuPool.FUList3.opList3] 345type=OpDesc 346eventq_index=0 |
|
| 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 | 347opClass=FloatDiv 348opLat=12 349pipelined=false 350 |
| 335[system.cpu.fuPool.FUList3.opList2] | 351[system.cpu.fuPool.FUList3.opList4] |
| 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc | 352type=OpDesc 353eventq_index=0 354opClass=FloatSqrt 355opLat=24 356pipelined=false 357 358[system.cpu.fuPool.FUList4] 359type=FUDesc |
| 344children=opList | 360children=opList0 opList1 |
| 345count=0 346eventq_index=0 | 361count=0 362eventq_index=0 |
| 347opList=system.cpu.fuPool.FUList4.opList | 363opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 |
| 348 | 364 |
| 349[system.cpu.fuPool.FUList4.opList] | 365[system.cpu.fuPool.FUList4.opList0] |
| 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 | 366type=OpDesc 367eventq_index=0 368opClass=MemRead 369opLat=1 370pipelined=true 371 |
| 372[system.cpu.fuPool.FUList4.opList1] 373type=OpDesc 374eventq_index=0 375opClass=FloatMemRead 376opLat=1 377pipelined=true 378 |
|
| 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc | 379[system.cpu.fuPool.FUList5] 380type=FUDesc 381children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 382count=4 383eventq_index=0 384opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 385 386[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 520type=OpDesc 521eventq_index=0 522opClass=SimdFloatSqrt 523opLat=1 524pipelined=true 525 526[system.cpu.fuPool.FUList6] 527type=FUDesc |
| 505children=opList | 528children=opList0 opList1 |
| 506count=0 507eventq_index=0 | 529count=0 530eventq_index=0 |
| 508opList=system.cpu.fuPool.FUList6.opList | 531opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 |
| 509 | 532 |
| 510[system.cpu.fuPool.FUList6.opList] | 533[system.cpu.fuPool.FUList6.opList0] |
| 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 | 534type=OpDesc 535eventq_index=0 536opClass=MemWrite 537opLat=1 538pipelined=true 539 |
| 540[system.cpu.fuPool.FUList6.opList1] 541type=OpDesc 542eventq_index=0 543opClass=FloatMemWrite 544opLat=1 545pipelined=true 546 |
|
| 517[system.cpu.fuPool.FUList7] 518type=FUDesc | 547[system.cpu.fuPool.FUList7] 548type=FUDesc |
| 519children=opList0 opList1 | 549children=opList0 opList1 opList2 opList3 |
| 520count=4 521eventq_index=0 | 550count=4 551eventq_index=0 |
| 522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 | 552opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 |
| 523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 | 553 554[system.cpu.fuPool.FUList7.opList0] 555type=OpDesc 556eventq_index=0 557opClass=MemRead 558opLat=1 559pipelined=true 560 561[system.cpu.fuPool.FUList7.opList1] 562type=OpDesc 563eventq_index=0 564opClass=MemWrite 565opLat=1 566pipelined=true 567 |
| 568[system.cpu.fuPool.FUList7.opList2] 569type=OpDesc 570eventq_index=0 571opClass=FloatMemRead 572opLat=1 573pipelined=true 574 575[system.cpu.fuPool.FUList7.opList3] 576type=OpDesc 577eventq_index=0 578opClass=FloatMemWrite 579opLat=1 580pipelined=true 581 |
|
| 538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615:0:0:0:0 556assoc=2 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl | 582[system.cpu.fuPool.FUList8] 583type=FUDesc 584children=opList 585count=1 586eventq_index=0 587opList=system.cpu.fuPool.FUList8.opList 588 589[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 595 596[system.cpu.icache] 597type=Cache 598children=tags 599addr_ranges=0:18446744073709551615:0:0:0:0 600assoc=2 601clk_domain=system.cpu_clk_domain 602clusivity=mostly_incl |
| 603data_latency=2 |
|
| 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 | 604default_p_state=UNDEFINED 605demand_mshr_reserve=1 606eventq_index=0 |
| 562hit_latency=2 | |
| 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=131072 575system=system | 607is_read_only=true 608max_miss_count=0 609mshrs=4 610p_state_clk_gate_bins=20 611p_state_clk_gate_max=1000000000000 612p_state_clk_gate_min=1000 613power_model=Null 614prefetch_on_access=false 615prefetcher=Null 616response_latency=2 617sequential_access=false 618size=131072 619system=system |
| 620tag_latency=2 |
|
| 576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=2 586block_size=64 587clk_domain=system.cpu_clk_domain | 621tags=system.cpu.icache.tags 622tgts_per_mshr=20 623write_buffers=8 624writeback_clean=true 625cpu_side=system.cpu.icache_port 626mem_side=system.cpu.toL2Bus.slave[0] 627 628[system.cpu.icache.tags] 629type=LRU 630assoc=2 631block_size=64 632clk_domain=system.cpu_clk_domain |
| 633data_latency=2 |
|
| 588default_p_state=UNDEFINED 589eventq_index=0 | 634default_p_state=UNDEFINED 635eventq_index=0 |
| 590hit_latency=2 | |
| 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=131072 | 636p_state_clk_gate_bins=20 637p_state_clk_gate_max=1000000000000 638p_state_clk_gate_min=1000 639power_model=Null 640sequential_access=false 641size=131072 |
| 642tag_latency=2 |
|
| 597 598[system.cpu.interrupts] 599type=X86LocalApic 600clk_domain=system.cpu.apic_clk_domain 601default_p_state=UNDEFINED 602eventq_index=0 603int_latency=1000 604p_state_clk_gate_bins=20 --- 33 unchanged lines hidden (view full) --- 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615:0:0:0:0 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl | 643 644[system.cpu.interrupts] 645type=X86LocalApic 646clk_domain=system.cpu.apic_clk_domain 647default_p_state=UNDEFINED 648eventq_index=0 649int_latency=1000 650p_state_clk_gate_bins=20 --- 33 unchanged lines hidden (view full) --- 684 685[system.cpu.l2cache] 686type=Cache 687children=tags 688addr_ranges=0:18446744073709551615:0:0:0:0 689assoc=8 690clk_domain=system.cpu_clk_domain 691clusivity=mostly_incl |
| 692data_latency=20 |
|
| 646default_p_state=UNDEFINED 647demand_mshr_reserve=1 648eventq_index=0 | 693default_p_state=UNDEFINED 694demand_mshr_reserve=1 695eventq_index=0 |
| 649hit_latency=20 | |
| 650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system | 696is_read_only=false 697max_miss_count=0 698mshrs=20 699p_state_clk_gate_bins=20 700p_state_clk_gate_max=1000000000000 701p_state_clk_gate_min=1000 702power_model=Null 703prefetch_on_access=false 704prefetcher=Null 705response_latency=20 706sequential_access=false 707size=2097152 708system=system |
| 709tag_latency=20 |
|
| 663tags=system.cpu.l2cache.tags 664tgts_per_mshr=12 665write_buffers=8 666writeback_clean=false 667cpu_side=system.cpu.toL2Bus.master[0] 668mem_side=system.membus.slave[1] 669 670[system.cpu.l2cache.tags] 671type=LRU 672assoc=8 673block_size=64 674clk_domain=system.cpu_clk_domain | 710tags=system.cpu.l2cache.tags 711tgts_per_mshr=12 712write_buffers=8 713writeback_clean=false 714cpu_side=system.cpu.toL2Bus.master[0] 715mem_side=system.membus.slave[1] 716 717[system.cpu.l2cache.tags] 718type=LRU 719assoc=8 720block_size=64 721clk_domain=system.cpu_clk_domain |
| 722data_latency=20 |
|
| 675default_p_state=UNDEFINED 676eventq_index=0 | 723default_p_state=UNDEFINED 724eventq_index=0 |
| 677hit_latency=20 | |
| 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682sequential_access=false 683size=2097152 | 725p_state_clk_gate_bins=20 726p_state_clk_gate_max=1000000000000 727p_state_clk_gate_min=1000 728power_model=Null 729sequential_access=false 730size=2097152 |
| 731tag_latency=20 |
|
| 684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 --- 28 unchanged lines hidden (view full) --- 720cmd=hello 721cwd= 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0 | 732 733[system.cpu.toL2Bus] 734type=CoherentXBar 735children=snoop_filter 736clk_domain=system.cpu_clk_domain 737default_p_state=UNDEFINED 738eventq_index=0 739forward_latency=0 --- 28 unchanged lines hidden (view full) --- 768cmd=hello 769cwd= 770drivers= 771egid=100 772env= 773errout=cerr 774euid=100 775eventq_index=0 |
| 728executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello | 776executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello |
| 729gid=100 730input=cin 731kvmInSE=false 732max_stack_size=67108864 733output=cout 734pid=100 735ppid=99 736simpoint=0 --- 137 unchanged lines hidden --- | 777gid=100 778input=cin 779kvmInSE=false 780max_stack_size=67108864 781output=cout 782pid=100 783ppid=99 784simpoint=0 --- 137 unchanged lines hidden --- |