config.ini (10036:80e84beef3bb) | config.ini (10242:cb4e86c17767) |
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1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 4 unchanged lines hidden (view full) --- 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 4 unchanged lines hidden (view full) --- 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 |
21load_offset=0 |
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21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 --- 81 unchanged lines hidden (view full) --- 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 | 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 --- 81 unchanged lines hidden (view full) --- 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 |
119socket_id=0 |
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118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 --- 501 unchanged lines hidden (view full) --- 627type=LiveProcess 628cmd=hello 629cwd= 630egid=100 631env= 632errout=cerr 633euid=100 634eventq_index=0 | 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 --- 501 unchanged lines hidden (view full) --- 629type=LiveProcess 630cmd=hello 631cwd= 632egid=100 633env= 634errout=cerr 635euid=100 636eventq_index=0 |
635executable=/dist/test-progs/hello/bin/x86/linux/hello | 637executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello |
636gid=100 637input=cin 638max_stack_size=67108864 639output=cout 640pid=100 641ppid=99 642simpoint=0 643system=system --- 12 unchanged lines hidden (view full) --- 656header_cycles=1 657system=system 658use_default_range=false 659width=8 660master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 661slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 662 663[system.physmem] | 638gid=100 639input=cin 640max_stack_size=67108864 641output=cout 642pid=100 643ppid=99 644simpoint=0 645system=system --- 12 unchanged lines hidden (view full) --- 658header_cycles=1 659system=system 660use_default_range=false 661width=8 662master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 663slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 664 665[system.physmem] |
664type=SimpleDRAM | 666type=DRAMCtrl |
665activation_limit=4 | 667activation_limit=4 |
666addr_mapping=RaBaChCo | 668addr_mapping=RoRaBaChCo |
667banks_per_rank=8 668burst_length=8 669channels=1 670clk_domain=system.clk_domain 671conf_table_reported=true 672device_bus_width=8 673device_rowbuffer_size=1024 674devices_per_rank=8 675eventq_index=0 676in_addr_map=true | 669banks_per_rank=8 670burst_length=8 671channels=1 672clk_domain=system.clk_domain 673conf_table_reported=true 674device_bus_width=8 675device_rowbuffer_size=1024 676devices_per_rank=8 677eventq_index=0 678in_addr_map=true |
679max_accesses_per_row=16 |
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677mem_sched_policy=frfcfs | 680mem_sched_policy=frfcfs |
681min_writes_per_switch=16 |
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678null=false | 682null=false |
679page_policy=open | 683page_policy=open_adaptive |
680range=0:134217727 681ranks_per_channel=2 682read_buffer_size=32 683static_backend_latency=10000 684static_frontend_latency=10000 685tBURST=5000 | 684range=0:134217727 685ranks_per_channel=2 686read_buffer_size=32 687static_backend_latency=10000 688static_frontend_latency=10000 689tBURST=5000 |
690tCK=1250 |
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686tCL=13750 687tRAS=35000 688tRCD=13750 689tREFI=7800000 | 691tCL=13750 692tRAS=35000 693tRCD=13750 694tREFI=7800000 |
690tRFC=300000 | 695tRFC=260000 |
691tRP=13750 | 696tRP=13750 |
692tRRD=6250 | 697tRRD=6000 698tRTP=7500 699tRTW=2500 700tWR=15000 |
693tWTR=7500 | 701tWTR=7500 |
694tXAW=40000 695write_buffer_size=32 696write_high_thresh_perc=70 697write_low_thresh_perc=0 | 702tXAW=30000 703write_buffer_size=64 704write_high_thresh_perc=85 705write_low_thresh_perc=50 |
698port=system.membus.master[0] 699 700[system.voltage_domain] 701type=VoltageDomain 702eventq_index=0 703voltage=1.000000 704 | 706port=system.membus.master[0] 707 708[system.voltage_domain] 709type=VoltageDomain 710eventq_index=0 711voltage=1.000000 712 |