| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 169 unchanged lines hidden (view full) --- 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl |
| 186data_latency=2 |
| 187default_p_state=UNDEFINED 188demand_mshr_reserve=1 189eventq_index=0 |
| 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system |
| 203tag_latency=2 |
| 204tags=system.cpu.dcache.tags 205tgts_per_mshr=20 206write_buffers=8 207writeback_clean=false 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dcache.tags] 212type=LRU 213assoc=2 214block_size=64 215clk_domain=system.cpu_clk_domain |
| 216data_latency=2 |
| 217default_p_state=UNDEFINED 218eventq_index=0 |
| 219p_state_clk_gate_bins=20 220p_state_clk_gate_max=1000000000000 221p_state_clk_gate_min=1000 222power_model=Null 223sequential_access=false 224size=262144 |
| 225tag_latency=2 |
| 226 227[system.cpu.dtb] 228type=X86TLB 229children=walker 230eventq_index=0 231size=64 232walker=system.cpu.dtb.walker 233 --- 76 unchanged lines hidden (view full) --- 310type=OpDesc 311eventq_index=0 312opClass=FloatCvt 313opLat=2 314pipelined=true 315 316[system.cpu.fuPool.FUList3] 317type=FUDesc |
| 318children=opList0 opList1 opList2 opList3 opList4 |
| 319count=2 320eventq_index=0 |
| 321opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 |
| 322 323[system.cpu.fuPool.FUList3.opList0] 324type=OpDesc 325eventq_index=0 326opClass=FloatMult 327opLat=4 328pipelined=true 329 330[system.cpu.fuPool.FUList3.opList1] 331type=OpDesc 332eventq_index=0 |
| 333opClass=FloatMultAcc 334opLat=5 335pipelined=true 336 337[system.cpu.fuPool.FUList3.opList2] 338type=OpDesc 339eventq_index=0 340opClass=FloatMisc 341opLat=3 342pipelined=true 343 344[system.cpu.fuPool.FUList3.opList3] 345type=OpDesc 346eventq_index=0 |
| 347opClass=FloatDiv 348opLat=12 349pipelined=false 350 |
| 351[system.cpu.fuPool.FUList3.opList4] |
| 352type=OpDesc 353eventq_index=0 354opClass=FloatSqrt 355opLat=24 356pipelined=false 357 358[system.cpu.fuPool.FUList4] 359type=FUDesc |
| 360children=opList0 opList1 |
| 361count=0 362eventq_index=0 |
| 363opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 |
| 364 |
| 365[system.cpu.fuPool.FUList4.opList0] |
| 366type=OpDesc 367eventq_index=0 368opClass=MemRead 369opLat=1 370pipelined=true 371 |
| 372[system.cpu.fuPool.FUList4.opList1] 373type=OpDesc 374eventq_index=0 375opClass=FloatMemRead 376opLat=1 377pipelined=true 378 |
| 379[system.cpu.fuPool.FUList5] 380type=FUDesc 381children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 382count=4 383eventq_index=0 384opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 385 386[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 520type=OpDesc 521eventq_index=0 522opClass=SimdFloatSqrt 523opLat=1 524pipelined=true 525 526[system.cpu.fuPool.FUList6] 527type=FUDesc |
| 528children=opList0 opList1 |
| 529count=0 530eventq_index=0 |
| 531opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 |
| 532 |
| 533[system.cpu.fuPool.FUList6.opList0] |
| 534type=OpDesc 535eventq_index=0 536opClass=MemWrite 537opLat=1 538pipelined=true 539 |
| 540[system.cpu.fuPool.FUList6.opList1] 541type=OpDesc 542eventq_index=0 543opClass=FloatMemWrite 544opLat=1 545pipelined=true 546 |
| 547[system.cpu.fuPool.FUList7] 548type=FUDesc |
| 549children=opList0 opList1 opList2 opList3 |
| 550count=4 551eventq_index=0 |
| 552opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 |
| 553 554[system.cpu.fuPool.FUList7.opList0] 555type=OpDesc 556eventq_index=0 557opClass=MemRead 558opLat=1 559pipelined=true 560 561[system.cpu.fuPool.FUList7.opList1] 562type=OpDesc 563eventq_index=0 564opClass=MemWrite 565opLat=1 566pipelined=true 567 |
| 568[system.cpu.fuPool.FUList7.opList2] 569type=OpDesc 570eventq_index=0 571opClass=FloatMemRead 572opLat=1 573pipelined=true 574 575[system.cpu.fuPool.FUList7.opList3] 576type=OpDesc 577eventq_index=0 578opClass=FloatMemWrite 579opLat=1 580pipelined=true 581 |
| 582[system.cpu.fuPool.FUList8] 583type=FUDesc 584children=opList 585count=1 586eventq_index=0 587opList=system.cpu.fuPool.FUList8.opList 588 589[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 595 596[system.cpu.icache] 597type=Cache 598children=tags 599addr_ranges=0:18446744073709551615:0:0:0:0 600assoc=2 601clk_domain=system.cpu_clk_domain 602clusivity=mostly_incl |
| 603data_latency=2 |
| 604default_p_state=UNDEFINED 605demand_mshr_reserve=1 606eventq_index=0 |
| 607is_read_only=true 608max_miss_count=0 609mshrs=4 610p_state_clk_gate_bins=20 611p_state_clk_gate_max=1000000000000 612p_state_clk_gate_min=1000 613power_model=Null 614prefetch_on_access=false 615prefetcher=Null 616response_latency=2 617sequential_access=false 618size=131072 619system=system |
| 620tag_latency=2 |
| 621tags=system.cpu.icache.tags 622tgts_per_mshr=20 623write_buffers=8 624writeback_clean=true 625cpu_side=system.cpu.icache_port 626mem_side=system.cpu.toL2Bus.slave[0] 627 628[system.cpu.icache.tags] 629type=LRU 630assoc=2 631block_size=64 632clk_domain=system.cpu_clk_domain |
| 633data_latency=2 |
| 634default_p_state=UNDEFINED 635eventq_index=0 |
| 636p_state_clk_gate_bins=20 637p_state_clk_gate_max=1000000000000 638p_state_clk_gate_min=1000 639power_model=Null 640sequential_access=false 641size=131072 |
| 642tag_latency=2 |
| 643 644[system.cpu.interrupts] 645type=X86LocalApic 646clk_domain=system.cpu.apic_clk_domain 647default_p_state=UNDEFINED 648eventq_index=0 649int_latency=1000 650p_state_clk_gate_bins=20 --- 33 unchanged lines hidden (view full) --- 684 685[system.cpu.l2cache] 686type=Cache 687children=tags 688addr_ranges=0:18446744073709551615:0:0:0:0 689assoc=8 690clk_domain=system.cpu_clk_domain 691clusivity=mostly_incl |
| 692data_latency=20 |
| 693default_p_state=UNDEFINED 694demand_mshr_reserve=1 695eventq_index=0 |
| 696is_read_only=false 697max_miss_count=0 698mshrs=20 699p_state_clk_gate_bins=20 700p_state_clk_gate_max=1000000000000 701p_state_clk_gate_min=1000 702power_model=Null 703prefetch_on_access=false 704prefetcher=Null 705response_latency=20 706sequential_access=false 707size=2097152 708system=system |
| 709tag_latency=20 |
| 710tags=system.cpu.l2cache.tags 711tgts_per_mshr=12 712write_buffers=8 713writeback_clean=false 714cpu_side=system.cpu.toL2Bus.master[0] 715mem_side=system.membus.slave[1] 716 717[system.cpu.l2cache.tags] 718type=LRU 719assoc=8 720block_size=64 721clk_domain=system.cpu_clk_domain |
| 722data_latency=20 |
| 723default_p_state=UNDEFINED 724eventq_index=0 |
| 725p_state_clk_gate_bins=20 726p_state_clk_gate_max=1000000000000 727p_state_clk_gate_min=1000 728power_model=Null 729sequential_access=false 730size=2097152 |
| 731tag_latency=20 |
| 732 733[system.cpu.toL2Bus] 734type=CoherentXBar 735children=snoop_filter 736clk_domain=system.cpu_clk_domain 737default_p_state=UNDEFINED 738eventq_index=0 739forward_latency=0 --- 28 unchanged lines hidden (view full) --- 768cmd=hello 769cwd= 770drivers= 771egid=100 772env= 773errout=cerr 774euid=100 775eventq_index=0 |
| 776executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello |
| 777gid=100 778input=cin 779kvmInSE=false 780max_stack_size=67108864 781output=cout 782pid=100 783ppid=99 784simpoint=0 --- 137 unchanged lines hidden --- |