| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 151 unchanged lines hidden (view full) --- 160children=tags 161addr_ranges=0:18446744073709551615 162assoc=2 163clk_domain=system.cpu_clk_domain 164demand_mshr_reserve=1 165eventq_index=0 166forward_snoops=true 167hit_latency=2 |
| 168is_read_only=false |
| 169max_miss_count=0 170mshrs=4 171prefetch_on_access=false 172prefetcher=Null 173response_latency=2 174sequential_access=false 175size=262144 176system=system 177tags=system.cpu.dcache.tags 178tgts_per_mshr=20 |
| 179write_buffers=8 180cpu_side=system.cpu.dcache_port 181mem_side=system.cpu.toL2Bus.slave[1] 182 183[system.cpu.dcache.tags] 184type=LRU 185assoc=2 186block_size=64 --- 29 unchanged lines hidden (view full) --- 216children=opList 217count=6 218eventq_index=0 219opList=system.cpu.fuPool.FUList0.opList 220 221[system.cpu.fuPool.FUList0.opList] 222type=OpDesc 223eventq_index=0 |
| 224opClass=IntAlu 225opLat=1 |
| 226pipelined=true |
| 227 228[system.cpu.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232eventq_index=0 233opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 234 235[system.cpu.fuPool.FUList1.opList0] 236type=OpDesc 237eventq_index=0 |
| 238opClass=IntMult 239opLat=3 |
| 240pipelined=true |
| 241 242[system.cpu.fuPool.FUList1.opList1] 243type=OpDesc 244eventq_index=0 |
| 245opClass=IntDiv |
| 246opLat=1 247pipelined=false |
| 248 249[system.cpu.fuPool.FUList2] 250type=FUDesc 251children=opList0 opList1 opList2 252count=4 253eventq_index=0 254opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 255 256[system.cpu.fuPool.FUList2.opList0] 257type=OpDesc 258eventq_index=0 |
| 259opClass=FloatAdd 260opLat=2 |
| 261pipelined=true |
| 262 263[system.cpu.fuPool.FUList2.opList1] 264type=OpDesc 265eventq_index=0 |
| 266opClass=FloatCmp 267opLat=2 |
| 268pipelined=true |
| 269 270[system.cpu.fuPool.FUList2.opList2] 271type=OpDesc 272eventq_index=0 |
| 273opClass=FloatCvt 274opLat=2 |
| 275pipelined=true |
| 276 277[system.cpu.fuPool.FUList3] 278type=FUDesc 279children=opList0 opList1 opList2 280count=2 281eventq_index=0 282opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 283 284[system.cpu.fuPool.FUList3.opList0] 285type=OpDesc 286eventq_index=0 |
| 287opClass=FloatMult 288opLat=4 |
| 289pipelined=true |
| 290 291[system.cpu.fuPool.FUList3.opList1] 292type=OpDesc 293eventq_index=0 |
| 294opClass=FloatDiv 295opLat=12 |
| 296pipelined=false |
| 297 298[system.cpu.fuPool.FUList3.opList2] 299type=OpDesc 300eventq_index=0 |
| 301opClass=FloatSqrt 302opLat=24 |
| 303pipelined=false |
| 304 305[system.cpu.fuPool.FUList4] 306type=FUDesc 307children=opList 308count=0 309eventq_index=0 310opList=system.cpu.fuPool.FUList4.opList 311 312[system.cpu.fuPool.FUList4.opList] 313type=OpDesc 314eventq_index=0 |
| 315opClass=MemRead 316opLat=1 |
| 317pipelined=true |
| 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323eventq_index=0 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328eventq_index=0 |
| 329opClass=SimdAdd 330opLat=1 |
| 331pipelined=true |
| 332 333[system.cpu.fuPool.FUList5.opList01] 334type=OpDesc 335eventq_index=0 |
| 336opClass=SimdAddAcc 337opLat=1 |
| 338pipelined=true |
| 339 340[system.cpu.fuPool.FUList5.opList02] 341type=OpDesc 342eventq_index=0 |
| 343opClass=SimdAlu 344opLat=1 |
| 345pipelined=true |
| 346 347[system.cpu.fuPool.FUList5.opList03] 348type=OpDesc 349eventq_index=0 |
| 350opClass=SimdCmp 351opLat=1 |
| 352pipelined=true |
| 353 354[system.cpu.fuPool.FUList5.opList04] 355type=OpDesc 356eventq_index=0 |
| 357opClass=SimdCvt 358opLat=1 |
| 359pipelined=true |
| 360 361[system.cpu.fuPool.FUList5.opList05] 362type=OpDesc 363eventq_index=0 |
| 364opClass=SimdMisc 365opLat=1 |
| 366pipelined=true |
| 367 368[system.cpu.fuPool.FUList5.opList06] 369type=OpDesc 370eventq_index=0 |
| 371opClass=SimdMult 372opLat=1 |
| 373pipelined=true |
| 374 375[system.cpu.fuPool.FUList5.opList07] 376type=OpDesc 377eventq_index=0 |
| 378opClass=SimdMultAcc 379opLat=1 |
| 380pipelined=true |
| 381 382[system.cpu.fuPool.FUList5.opList08] 383type=OpDesc 384eventq_index=0 |
| 385opClass=SimdShift 386opLat=1 |
| 387pipelined=true |
| 388 389[system.cpu.fuPool.FUList5.opList09] 390type=OpDesc 391eventq_index=0 |
| 392opClass=SimdShiftAcc 393opLat=1 |
| 394pipelined=true |
| 395 396[system.cpu.fuPool.FUList5.opList10] 397type=OpDesc 398eventq_index=0 |
| 399opClass=SimdSqrt 400opLat=1 |
| 401pipelined=true |
| 402 403[system.cpu.fuPool.FUList5.opList11] 404type=OpDesc 405eventq_index=0 |
| 406opClass=SimdFloatAdd 407opLat=1 |
| 408pipelined=true |
| 409 410[system.cpu.fuPool.FUList5.opList12] 411type=OpDesc 412eventq_index=0 |
| 413opClass=SimdFloatAlu 414opLat=1 |
| 415pipelined=true |
| 416 417[system.cpu.fuPool.FUList5.opList13] 418type=OpDesc 419eventq_index=0 |
| 420opClass=SimdFloatCmp 421opLat=1 |
| 422pipelined=true |
| 423 424[system.cpu.fuPool.FUList5.opList14] 425type=OpDesc 426eventq_index=0 |
| 427opClass=SimdFloatCvt 428opLat=1 |
| 429pipelined=true |
| 430 431[system.cpu.fuPool.FUList5.opList15] 432type=OpDesc 433eventq_index=0 |
| 434opClass=SimdFloatDiv 435opLat=1 |
| 436pipelined=true |
| 437 438[system.cpu.fuPool.FUList5.opList16] 439type=OpDesc 440eventq_index=0 |
| 441opClass=SimdFloatMisc 442opLat=1 |
| 443pipelined=true |
| 444 445[system.cpu.fuPool.FUList5.opList17] 446type=OpDesc 447eventq_index=0 |
| 448opClass=SimdFloatMult 449opLat=1 |
| 450pipelined=true |
| 451 452[system.cpu.fuPool.FUList5.opList18] 453type=OpDesc 454eventq_index=0 |
| 455opClass=SimdFloatMultAcc 456opLat=1 |
| 457pipelined=true |
| 458 459[system.cpu.fuPool.FUList5.opList19] 460type=OpDesc 461eventq_index=0 |
| 462opClass=SimdFloatSqrt 463opLat=1 |
| 464pipelined=true |
| 465 466[system.cpu.fuPool.FUList6] 467type=FUDesc 468children=opList 469count=0 470eventq_index=0 471opList=system.cpu.fuPool.FUList6.opList 472 473[system.cpu.fuPool.FUList6.opList] 474type=OpDesc 475eventq_index=0 |
| 476opClass=MemWrite 477opLat=1 |
| 478pipelined=true |
| 479 480[system.cpu.fuPool.FUList7] 481type=FUDesc 482children=opList0 opList1 483count=4 484eventq_index=0 485opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 486 487[system.cpu.fuPool.FUList7.opList0] 488type=OpDesc 489eventq_index=0 |
| 490opClass=MemRead 491opLat=1 |
| 492pipelined=true |
| 493 494[system.cpu.fuPool.FUList7.opList1] 495type=OpDesc 496eventq_index=0 |
| 497opClass=MemWrite 498opLat=1 |
| 499pipelined=true |
| 500 501[system.cpu.fuPool.FUList8] 502type=FUDesc 503children=opList 504count=1 505eventq_index=0 506opList=system.cpu.fuPool.FUList8.opList 507 508[system.cpu.fuPool.FUList8.opList] 509type=OpDesc 510eventq_index=0 |
| 511opClass=IprAccess 512opLat=3 |
| 513pipelined=false |
| 514 515[system.cpu.icache] 516type=BaseCache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=2 520clk_domain=system.cpu_clk_domain 521demand_mshr_reserve=1 522eventq_index=0 523forward_snoops=true 524hit_latency=2 |
| 525is_read_only=true |
| 526max_miss_count=0 527mshrs=4 528prefetch_on_access=false 529prefetcher=Null 530response_latency=2 531sequential_access=false 532size=131072 533system=system 534tags=system.cpu.icache.tags 535tgts_per_mshr=20 |
| 536write_buffers=8 537cpu_side=system.cpu.icache_port 538mem_side=system.cpu.toL2Bus.slave[0] 539 540[system.cpu.icache.tags] 541type=LRU 542assoc=2 543block_size=64 --- 39 unchanged lines hidden (view full) --- 583children=tags 584addr_ranges=0:18446744073709551615 585assoc=8 586clk_domain=system.cpu_clk_domain 587demand_mshr_reserve=1 588eventq_index=0 589forward_snoops=true 590hit_latency=20 |
| 591is_read_only=false |
| 592max_miss_count=0 593mshrs=20 594prefetch_on_access=false 595prefetcher=Null 596response_latency=20 597sequential_access=false 598size=2097152 599system=system 600tags=system.cpu.l2cache.tags 601tgts_per_mshr=12 |
| 602write_buffers=8 603cpu_side=system.cpu.toL2Bus.master[0] 604mem_side=system.membus.slave[1] 605 606[system.cpu.l2cache.tags] 607type=LRU 608assoc=8 609block_size=64 --- 161 unchanged lines hidden --- |