19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[0]
---
> system_port=system.membus.slave[0]
130c129
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
151c150
< mem_side=system.cpu.toL2Bus.port[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
162c161
< port=system.cpu.toL2Bus.port[3]
---
> port=system.cpu.toL2Bus.slave[3]
429c428
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
450c449
< mem_side=system.cpu.toL2Bus.port[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
458,459c457,459
< int_port=system.membus.port[4]
< pio=system.membus.port[3]
---
> int_master=system.membus.slave[2]
> int_slave=system.membus.master[2]
> pio=system.membus.master[1]
470c470
< port=system.cpu.toL2Bus.port[2]
---
> port=system.cpu.toL2Bus.slave[2]
474c474
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
494,495c494,495
< cpu_side=system.cpu.toL2Bus.port[4]
< mem_side=system.membus.port[2]
---
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[1]
505c505,506
< port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
---
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
537c538,539
< port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
---
> master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
> slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
540c542,543
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
541a545
> in_addr_map=true
547c551
< port=system.membus.port[1]
---
> port=system.membus.master[0]