Cross Reference: /gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini

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config.ini (9276:a5ede748a1d9)	config.ini (9348:44d31345e360)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a
13clock=1	13clock=1000
14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU	14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload	33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts	34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts
	81isa=system.cpu.isa
81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=true 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64	82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=true 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64
132clock=1	133clock=500
133forward_snoops=true 134hash_delay=1	134forward_snoops=true 135hash_delay=1
135hit_latency=1000	136hit_latency=2
136is_top_level=true 137max_miss_count=0	137is_top_level=true 138max_miss_count=0
138mshrs=10	139mshrs=4
139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null	140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null
143response_latency=1000	144response_latency=2
144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port 152mem_side=system.cpu.toL2Bus.slave[1] 153 154[system.cpu.dtb] 155type=X86TLB 156children=walker 157size=64 158walker=system.cpu.dtb.walker 159 160[system.cpu.dtb.walker] 161type=X86PagetableWalker	145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port 153mem_side=system.cpu.toL2Bus.slave[1] 154 155[system.cpu.dtb] 156type=X86TLB 157children=walker 158size=64 159walker=system.cpu.dtb.walker 160 161[system.cpu.dtb.walker] 162type=X86PagetableWalker
162clock=1	163clock=500
163system=system 164port=system.cpu.toL2Bus.slave[3] 165 166[system.cpu.fuPool] 167type=FUPool 168children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 169FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 170 171[system.cpu.fuPool.FUList0] 172type=FUDesc 173children=opList 174count=6 175opList=system.cpu.fuPool.FUList0.opList 176 177[system.cpu.fuPool.FUList0.opList] 178type=OpDesc 179issueLat=1 180opClass=IntAlu 181opLat=1 182 183[system.cpu.fuPool.FUList1] 184type=FUDesc 185children=opList0 opList1 186count=2 187opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 188 189[system.cpu.fuPool.FUList1.opList0] 190type=OpDesc 191issueLat=1 192opClass=IntMult 193opLat=3 194 195[system.cpu.fuPool.FUList1.opList1] 196type=OpDesc 197issueLat=19 198opClass=IntDiv 199opLat=20 200 201[system.cpu.fuPool.FUList2] 202type=FUDesc 203children=opList0 opList1 opList2 204count=4 205opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 206 207[system.cpu.fuPool.FUList2.opList0] 208type=OpDesc 209issueLat=1 210opClass=FloatAdd 211opLat=2 212 213[system.cpu.fuPool.FUList2.opList1] 214type=OpDesc 215issueLat=1 216opClass=FloatCmp 217opLat=2 218 219[system.cpu.fuPool.FUList2.opList2] 220type=OpDesc 221issueLat=1 222opClass=FloatCvt 223opLat=2 224 225[system.cpu.fuPool.FUList3] 226type=FUDesc 227children=opList0 opList1 opList2 228count=2 229opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 230 231[system.cpu.fuPool.FUList3.opList0] 232type=OpDesc 233issueLat=1 234opClass=FloatMult 235opLat=4 236 237[system.cpu.fuPool.FUList3.opList1] 238type=OpDesc 239issueLat=12 240opClass=FloatDiv 241opLat=12 242 243[system.cpu.fuPool.FUList3.opList2] 244type=OpDesc 245issueLat=24 246opClass=FloatSqrt 247opLat=24 248 249[system.cpu.fuPool.FUList4] 250type=FUDesc 251children=opList 252count=0 253opList=system.cpu.fuPool.FUList4.opList 254 255[system.cpu.fuPool.FUList4.opList] 256type=OpDesc 257issueLat=1 258opClass=MemRead 259opLat=1 260 261[system.cpu.fuPool.FUList5] 262type=FUDesc 263children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 264count=4 265opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 266 267[system.cpu.fuPool.FUList5.opList00] 268type=OpDesc 269issueLat=1 270opClass=SimdAdd 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList01] 274type=OpDesc 275issueLat=1 276opClass=SimdAddAcc 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList02] 280type=OpDesc 281issueLat=1 282opClass=SimdAlu 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList03] 286type=OpDesc 287issueLat=1 288opClass=SimdCmp 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList04] 292type=OpDesc 293issueLat=1 294opClass=SimdCvt 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList05] 298type=OpDesc 299issueLat=1 300opClass=SimdMisc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList06] 304type=OpDesc 305issueLat=1 306opClass=SimdMult 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList07] 310type=OpDesc 311issueLat=1 312opClass=SimdMultAcc 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList08] 316type=OpDesc 317issueLat=1 318opClass=SimdShift 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList09] 322type=OpDesc 323issueLat=1 324opClass=SimdShiftAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList10] 328type=OpDesc 329issueLat=1 330opClass=SimdSqrt 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList11] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAdd 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList12] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAlu 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList13] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCmp 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList14] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCvt 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList15] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatDiv 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList16] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMisc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList17] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMult 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList18] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMultAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList19] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList6] 388type=FUDesc 389children=opList 390count=0 391opList=system.cpu.fuPool.FUList6.opList 392 393[system.cpu.fuPool.FUList6.opList] 394type=OpDesc 395issueLat=1 396opClass=MemWrite 397opLat=1 398 399[system.cpu.fuPool.FUList7] 400type=FUDesc 401children=opList0 opList1 402count=4 403opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 404 405[system.cpu.fuPool.FUList7.opList0] 406type=OpDesc 407issueLat=1 408opClass=MemRead 409opLat=1 410 411[system.cpu.fuPool.FUList7.opList1] 412type=OpDesc 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList8] 418type=FUDesc 419children=opList 420count=1 421opList=system.cpu.fuPool.FUList8.opList 422 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache 431addr_ranges=0:18446744073709551615 432assoc=2 433block_size=64	164system=system 165port=system.cpu.toL2Bus.slave[3] 166 167[system.cpu.fuPool] 168type=FUPool 169children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 170FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 171 172[system.cpu.fuPool.FUList0] 173type=FUDesc 174children=opList 175count=6 176opList=system.cpu.fuPool.FUList0.opList 177 178[system.cpu.fuPool.FUList0.opList] 179type=OpDesc 180issueLat=1 181opClass=IntAlu 182opLat=1 183 184[system.cpu.fuPool.FUList1] 185type=FUDesc 186children=opList0 opList1 187count=2 188opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 189 190[system.cpu.fuPool.FUList1.opList0] 191type=OpDesc 192issueLat=1 193opClass=IntMult 194opLat=3 195 196[system.cpu.fuPool.FUList1.opList1] 197type=OpDesc 198issueLat=19 199opClass=IntDiv 200opLat=20 201 202[system.cpu.fuPool.FUList2] 203type=FUDesc 204children=opList0 opList1 opList2 205count=4 206opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 207 208[system.cpu.fuPool.FUList2.opList0] 209type=OpDesc 210issueLat=1 211opClass=FloatAdd 212opLat=2 213 214[system.cpu.fuPool.FUList2.opList1] 215type=OpDesc 216issueLat=1 217opClass=FloatCmp 218opLat=2 219 220[system.cpu.fuPool.FUList2.opList2] 221type=OpDesc 222issueLat=1 223opClass=FloatCvt 224opLat=2 225 226[system.cpu.fuPool.FUList3] 227type=FUDesc 228children=opList0 opList1 opList2 229count=2 230opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 231 232[system.cpu.fuPool.FUList3.opList0] 233type=OpDesc 234issueLat=1 235opClass=FloatMult 236opLat=4 237 238[system.cpu.fuPool.FUList3.opList1] 239type=OpDesc 240issueLat=12 241opClass=FloatDiv 242opLat=12 243 244[system.cpu.fuPool.FUList3.opList2] 245type=OpDesc 246issueLat=24 247opClass=FloatSqrt 248opLat=24 249 250[system.cpu.fuPool.FUList4] 251type=FUDesc 252children=opList 253count=0 254opList=system.cpu.fuPool.FUList4.opList 255 256[system.cpu.fuPool.FUList4.opList] 257type=OpDesc 258issueLat=1 259opClass=MemRead 260opLat=1 261 262[system.cpu.fuPool.FUList5] 263type=FUDesc 264children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 265count=4 266opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 267 268[system.cpu.fuPool.FUList5.opList00] 269type=OpDesc 270issueLat=1 271opClass=SimdAdd 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList01] 275type=OpDesc 276issueLat=1 277opClass=SimdAddAcc 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList02] 281type=OpDesc 282issueLat=1 283opClass=SimdAlu 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList03] 287type=OpDesc 288issueLat=1 289opClass=SimdCmp 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList04] 293type=OpDesc 294issueLat=1 295opClass=SimdCvt 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList05] 299type=OpDesc 300issueLat=1 301opClass=SimdMisc 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList06] 305type=OpDesc 306issueLat=1 307opClass=SimdMult 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList07] 311type=OpDesc 312issueLat=1 313opClass=SimdMultAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList08] 317type=OpDesc 318issueLat=1 319opClass=SimdShift 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList09] 323type=OpDesc 324issueLat=1 325opClass=SimdShiftAcc 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList10] 329type=OpDesc 330issueLat=1 331opClass=SimdSqrt 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList11] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatAdd 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList12] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatAlu 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList13] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatCmp 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList14] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatCvt 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList15] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatDiv 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList16] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMisc 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList17] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatMult 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList18] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatMultAcc 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList19] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatSqrt 386opLat=1 387 388[system.cpu.fuPool.FUList6] 389type=FUDesc 390children=opList 391count=0 392opList=system.cpu.fuPool.FUList6.opList 393 394[system.cpu.fuPool.FUList6.opList] 395type=OpDesc 396issueLat=1 397opClass=MemWrite 398opLat=1 399 400[system.cpu.fuPool.FUList7] 401type=FUDesc 402children=opList0 opList1 403count=4 404opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 405 406[system.cpu.fuPool.FUList7.opList0] 407type=OpDesc 408issueLat=1 409opClass=MemRead 410opLat=1 411 412[system.cpu.fuPool.FUList7.opList1] 413type=OpDesc 414issueLat=1 415opClass=MemWrite 416opLat=1 417 418[system.cpu.fuPool.FUList8] 419type=FUDesc 420children=opList 421count=1 422opList=system.cpu.fuPool.FUList8.opList 423 424[system.cpu.fuPool.FUList8.opList] 425type=OpDesc 426issueLat=3 427opClass=IprAccess 428opLat=3 429 430[system.cpu.icache] 431type=BaseCache 432addr_ranges=0:18446744073709551615 433assoc=2 434block_size=64
434clock=1	435clock=500
435forward_snoops=true 436hash_delay=1	436forward_snoops=true 437hash_delay=1
437hit_latency=1000	438hit_latency=2
438is_top_level=true 439max_miss_count=0	439is_top_level=true 440max_miss_count=0
440mshrs=10	441mshrs=4
441prefetch_on_access=false 442prefetcher=Null 443prioritizeRequests=false 444repl=Null	442prefetch_on_access=false 443prefetcher=Null 444prioritizeRequests=false 445repl=Null
445response_latency=1000	446response_latency=2
446size=131072 447subblock_size=0 448system=system 449tgts_per_mshr=20 450trace_addr=0 451two_queue=false 452write_buffers=8 453cpu_side=system.cpu.icache_port 454mem_side=system.cpu.toL2Bus.slave[0] 455 456[system.cpu.interrupts] 457type=X86LocalApic	447size=131072 448subblock_size=0 449system=system 450tgts_per_mshr=20 451trace_addr=0 452two_queue=false 453write_buffers=8 454cpu_side=system.cpu.icache_port 455mem_side=system.cpu.toL2Bus.slave[0] 456 457[system.cpu.interrupts] 458type=X86LocalApic
458clock=1	459clock=500
459int_latency=1000 460pio_addr=2305843009213693952 461pio_latency=100000 462system=system 463int_master=system.membus.slave[2] 464int_slave=system.membus.master[2] 465pio=system.membus.master[1] 466	460int_latency=1000 461pio_addr=2305843009213693952 462pio_latency=100000 463system=system 464int_master=system.membus.slave[2] 465int_slave=system.membus.master[2] 466pio=system.membus.master[1] 467
	468[system.cpu.isa] 469type=X86ISA 470
467[system.cpu.itb] 468type=X86TLB 469children=walker 470size=64 471walker=system.cpu.itb.walker 472 473[system.cpu.itb.walker] 474type=X86PagetableWalker	471[system.cpu.itb] 472type=X86TLB 473children=walker 474size=64 475walker=system.cpu.itb.walker 476 477[system.cpu.itb.walker] 478type=X86PagetableWalker
475clock=1	479clock=500
476system=system 477port=system.cpu.toL2Bus.slave[2] 478 479[system.cpu.l2cache] 480type=BaseCache 481addr_ranges=0:18446744073709551615	480system=system 481port=system.cpu.toL2Bus.slave[2] 482 483[system.cpu.l2cache] 484type=BaseCache 485addr_ranges=0:18446744073709551615
482assoc=2	486assoc=8
483block_size=64	487block_size=64
484clock=1	488clock=500
485forward_snoops=true 486hash_delay=1	489forward_snoops=true 490hash_delay=1
487hit_latency=1000	491hit_latency=20
488is_top_level=false 489max_miss_count=0	492is_top_level=false 493max_miss_count=0
490mshrs=10	494mshrs=20
491prefetch_on_access=false 492prefetcher=Null 493prioritizeRequests=false 494repl=Null	495prefetch_on_access=false 496prefetcher=Null 497prioritizeRequests=false 498repl=Null
495response_latency=1000	499response_latency=20
496size=2097152 497subblock_size=0 498system=system	500size=2097152 501subblock_size=0 502system=system
499tgts_per_mshr=5	503tgts_per_mshr=12
500trace_addr=0 501two_queue=false 502write_buffers=8 503cpu_side=system.cpu.toL2Bus.master[0] 504mem_side=system.membus.slave[1] 505 506[system.cpu.toL2Bus] 507type=CoherentBus 508block_size=64	504trace_addr=0 505two_queue=false 506write_buffers=8 507cpu_side=system.cpu.toL2Bus.master[0] 508mem_side=system.membus.slave[1] 509 510[system.cpu.toL2Bus] 511type=CoherentBus 512block_size=64
509clock=1000	513clock=500
510header_cycles=1 511use_default_range=false	514header_cycles=1 515use_default_range=false
512width=8	516width=32
513master=system.cpu.l2cache.cpu_side 514slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 515 516[system.cpu.tracer] 517type=ExeTracer 518 519[system.cpu.workload] 520type=LiveProcess 521cmd=hello 522cwd= 523egid=100 524env= 525errout=cerr 526euid=100	517master=system.cpu.l2cache.cpu_side 518slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 519 520[system.cpu.tracer] 521type=ExeTracer 522 523[system.cpu.workload] 524type=LiveProcess 525cmd=hello 526cwd= 527egid=100 528env= 529errout=cerr 530euid=100
527executable=tests/test-progs/hello/bin/x86/linux/hello	531executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello
528gid=100 529input=cin 530max_stack_size=67108864 531output=cout 532pid=100 533ppid=99 534simpoint=0 535system=system 536uid=100 537 538[system.membus] 539type=CoherentBus 540block_size=64 541clock=1000 542header_cycles=1 543use_default_range=false 544width=8 545master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 546slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 547 548[system.physmem]	532gid=100 533input=cin 534max_stack_size=67108864 535output=cout 536pid=100 537ppid=99 538simpoint=0 539system=system 540uid=100 541 542[system.membus] 543type=CoherentBus 544block_size=64 545clock=1000 546header_cycles=1 547use_default_range=false 548width=8 549master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 550slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 551 552[system.physmem]
549type=SimpleMemory 550bandwidth=73.000000 551clock=1	553type=SimpleDRAM 554addr_mapping=openmap 555banks_per_rank=8 556clock=1000
552conf_table_reported=false 553in_addr_map=true	557conf_table_reported=false 558in_addr_map=true
554latency=30000 555latency_var=0	559lines_per_rowbuffer=64 560mem_sched_policy=fcfs
556null=false	561null=false
	562page_policy=open
557range=0:134217727	563range=0:134217727
	564ranks_per_channel=2 565read_buffer_size=32 566tBURST=4000 567tCL=14000 568tRCD=14000 569tREFI=7800000 570tRFC=300000 571tRP=14000 572tWTR=1000 573write_buffer_size=32 574write_thresh_perc=70
558zero=false 559port=system.membus.master[0] 560	575zero=false 576port=system.membus.master[0] 577