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sdiff udiff text old ( 10798:74e3c7359393 ) new ( 10901:8cfa8dac39fe )
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1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 151 unchanged lines hidden (view full) ---

160children=tags
161addr_ranges=0:18446744073709551615
162assoc=2
163clk_domain=system.cpu_clk_domain
164demand_mshr_reserve=1
165eventq_index=0
166forward_snoops=true
167hit_latency=2
168is_top_level=true
169max_miss_count=0
170mshrs=4
171prefetch_on_access=false
172prefetcher=Null
173response_latency=2
174sequential_access=false
175size=262144
176system=system
177tags=system.cpu.dcache.tags
178tgts_per_mshr=20
179two_queue=false
180write_buffers=8
181cpu_side=system.cpu.dcache_port
182mem_side=system.cpu.toL2Bus.slave[1]
183
184[system.cpu.dcache.tags]
185type=LRU
186assoc=2
187block_size=64

--- 29 unchanged lines hidden (view full) ---

217children=opList
218count=6
219eventq_index=0
220opList=system.cpu.fuPool.FUList0.opList
221
222[system.cpu.fuPool.FUList0.opList]
223type=OpDesc
224eventq_index=0
225issueLat=1
226opClass=IntAlu
227opLat=1
228
229[system.cpu.fuPool.FUList1]
230type=FUDesc
231children=opList0 opList1
232count=2
233eventq_index=0
234opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
235
236[system.cpu.fuPool.FUList1.opList0]
237type=OpDesc
238eventq_index=0
239issueLat=1
240opClass=IntMult
241opLat=3
242
243[system.cpu.fuPool.FUList1.opList1]
244type=OpDesc
245eventq_index=0
246issueLat=19
247opClass=IntDiv
248opLat=20
249
250[system.cpu.fuPool.FUList2]
251type=FUDesc
252children=opList0 opList1 opList2
253count=4
254eventq_index=0
255opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
256
257[system.cpu.fuPool.FUList2.opList0]
258type=OpDesc
259eventq_index=0
260issueLat=1
261opClass=FloatAdd
262opLat=2
263
264[system.cpu.fuPool.FUList2.opList1]
265type=OpDesc
266eventq_index=0
267issueLat=1
268opClass=FloatCmp
269opLat=2
270
271[system.cpu.fuPool.FUList2.opList2]
272type=OpDesc
273eventq_index=0
274issueLat=1
275opClass=FloatCvt
276opLat=2
277
278[system.cpu.fuPool.FUList3]
279type=FUDesc
280children=opList0 opList1 opList2
281count=2
282eventq_index=0
283opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
284
285[system.cpu.fuPool.FUList3.opList0]
286type=OpDesc
287eventq_index=0
288issueLat=1
289opClass=FloatMult
290opLat=4
291
292[system.cpu.fuPool.FUList3.opList1]
293type=OpDesc
294eventq_index=0
295issueLat=12
296opClass=FloatDiv
297opLat=12
298
299[system.cpu.fuPool.FUList3.opList2]
300type=OpDesc
301eventq_index=0
302issueLat=24
303opClass=FloatSqrt
304opLat=24
305
306[system.cpu.fuPool.FUList4]
307type=FUDesc
308children=opList
309count=0
310eventq_index=0
311opList=system.cpu.fuPool.FUList4.opList
312
313[system.cpu.fuPool.FUList4.opList]
314type=OpDesc
315eventq_index=0
316issueLat=1
317opClass=MemRead
318opLat=1
319
320[system.cpu.fuPool.FUList5]
321type=FUDesc
322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
323count=4
324eventq_index=0
325opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
326
327[system.cpu.fuPool.FUList5.opList00]
328type=OpDesc
329eventq_index=0
330issueLat=1
331opClass=SimdAdd
332opLat=1
333
334[system.cpu.fuPool.FUList5.opList01]
335type=OpDesc
336eventq_index=0
337issueLat=1
338opClass=SimdAddAcc
339opLat=1
340
341[system.cpu.fuPool.FUList5.opList02]
342type=OpDesc
343eventq_index=0
344issueLat=1
345opClass=SimdAlu
346opLat=1
347
348[system.cpu.fuPool.FUList5.opList03]
349type=OpDesc
350eventq_index=0
351issueLat=1
352opClass=SimdCmp
353opLat=1
354
355[system.cpu.fuPool.FUList5.opList04]
356type=OpDesc
357eventq_index=0
358issueLat=1
359opClass=SimdCvt
360opLat=1
361
362[system.cpu.fuPool.FUList5.opList05]
363type=OpDesc
364eventq_index=0
365issueLat=1
366opClass=SimdMisc
367opLat=1
368
369[system.cpu.fuPool.FUList5.opList06]
370type=OpDesc
371eventq_index=0
372issueLat=1
373opClass=SimdMult
374opLat=1
375
376[system.cpu.fuPool.FUList5.opList07]
377type=OpDesc
378eventq_index=0
379issueLat=1
380opClass=SimdMultAcc
381opLat=1
382
383[system.cpu.fuPool.FUList5.opList08]
384type=OpDesc
385eventq_index=0
386issueLat=1
387opClass=SimdShift
388opLat=1
389
390[system.cpu.fuPool.FUList5.opList09]
391type=OpDesc
392eventq_index=0
393issueLat=1
394opClass=SimdShiftAcc
395opLat=1
396
397[system.cpu.fuPool.FUList5.opList10]
398type=OpDesc
399eventq_index=0
400issueLat=1
401opClass=SimdSqrt
402opLat=1
403
404[system.cpu.fuPool.FUList5.opList11]
405type=OpDesc
406eventq_index=0
407issueLat=1
408opClass=SimdFloatAdd
409opLat=1
410
411[system.cpu.fuPool.FUList5.opList12]
412type=OpDesc
413eventq_index=0
414issueLat=1
415opClass=SimdFloatAlu
416opLat=1
417
418[system.cpu.fuPool.FUList5.opList13]
419type=OpDesc
420eventq_index=0
421issueLat=1
422opClass=SimdFloatCmp
423opLat=1
424
425[system.cpu.fuPool.FUList5.opList14]
426type=OpDesc
427eventq_index=0
428issueLat=1
429opClass=SimdFloatCvt
430opLat=1
431
432[system.cpu.fuPool.FUList5.opList15]
433type=OpDesc
434eventq_index=0
435issueLat=1
436opClass=SimdFloatDiv
437opLat=1
438
439[system.cpu.fuPool.FUList5.opList16]
440type=OpDesc
441eventq_index=0
442issueLat=1
443opClass=SimdFloatMisc
444opLat=1
445
446[system.cpu.fuPool.FUList5.opList17]
447type=OpDesc
448eventq_index=0
449issueLat=1
450opClass=SimdFloatMult
451opLat=1
452
453[system.cpu.fuPool.FUList5.opList18]
454type=OpDesc
455eventq_index=0
456issueLat=1
457opClass=SimdFloatMultAcc
458opLat=1
459
460[system.cpu.fuPool.FUList5.opList19]
461type=OpDesc
462eventq_index=0
463issueLat=1
464opClass=SimdFloatSqrt
465opLat=1
466
467[system.cpu.fuPool.FUList6]
468type=FUDesc
469children=opList
470count=0
471eventq_index=0
472opList=system.cpu.fuPool.FUList6.opList
473
474[system.cpu.fuPool.FUList6.opList]
475type=OpDesc
476eventq_index=0
477issueLat=1
478opClass=MemWrite
479opLat=1
480
481[system.cpu.fuPool.FUList7]
482type=FUDesc
483children=opList0 opList1
484count=4
485eventq_index=0
486opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
487
488[system.cpu.fuPool.FUList7.opList0]
489type=OpDesc
490eventq_index=0
491issueLat=1
492opClass=MemRead
493opLat=1
494
495[system.cpu.fuPool.FUList7.opList1]
496type=OpDesc
497eventq_index=0
498issueLat=1
499opClass=MemWrite
500opLat=1
501
502[system.cpu.fuPool.FUList8]
503type=FUDesc
504children=opList
505count=1
506eventq_index=0
507opList=system.cpu.fuPool.FUList8.opList
508
509[system.cpu.fuPool.FUList8.opList]
510type=OpDesc
511eventq_index=0
512issueLat=3
513opClass=IprAccess
514opLat=3
515
516[system.cpu.icache]
517type=BaseCache
518children=tags
519addr_ranges=0:18446744073709551615
520assoc=2
521clk_domain=system.cpu_clk_domain
522demand_mshr_reserve=1
523eventq_index=0
524forward_snoops=true
525hit_latency=2
526is_top_level=true
527max_miss_count=0
528mshrs=4
529prefetch_on_access=false
530prefetcher=Null
531response_latency=2
532sequential_access=false
533size=131072
534system=system
535tags=system.cpu.icache.tags
536tgts_per_mshr=20
537two_queue=false
538write_buffers=8
539cpu_side=system.cpu.icache_port
540mem_side=system.cpu.toL2Bus.slave[0]
541
542[system.cpu.icache.tags]
543type=LRU
544assoc=2
545block_size=64

--- 39 unchanged lines hidden (view full) ---

585children=tags
586addr_ranges=0:18446744073709551615
587assoc=8
588clk_domain=system.cpu_clk_domain
589demand_mshr_reserve=1
590eventq_index=0
591forward_snoops=true
592hit_latency=20
593is_top_level=false
594max_miss_count=0
595mshrs=20
596prefetch_on_access=false
597prefetcher=Null
598response_latency=20
599sequential_access=false
600size=2097152
601system=system
602tags=system.cpu.l2cache.tags
603tgts_per_mshr=12
604two_queue=false
605write_buffers=8
606cpu_side=system.cpu.toL2Bus.master[0]
607mem_side=system.membus.slave[1]
608
609[system.cpu.l2cache.tags]
610type=LRU
611assoc=8
612block_size=64

--- 161 unchanged lines hidden ---