| stats.txt (9055:38f1926fb599) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28206000 # Number of ticks simulated 5final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29541000 # Number of ticks simulated 5final_tick 29541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 427855 # Simulator instruction rate (inst/s) 8host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2253599179 # Simulator tick rate (ticks/s) 10host_mem_usage 221156 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host | 7host_inst_rate 73924 # Simulator instruction rate (inst/s) 8host_op_rate 73907 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 408761366 # Simulator tick rate (ticks/s) 10host_mem_usage 220016 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 5340 # Number of instructions simulated 13sim_ops 5340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 389 # Number of read requests responded to by this memory | 12sim_insts 5340 # Number of instructions simulated 13sim_ops 5340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 389 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 552452524 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 290308385 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 842760909 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 552452524 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 552452524 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 552452524 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 290308385 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 842760909 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.workload.num_syscalls 11 # Number of system calls | 30system.cpu.workload.num_syscalls 11 # Number of system calls |
| 31system.cpu.numCycles 56412 # number of cpu cycles simulated | 31system.cpu.numCycles 59082 # number of cpu cycles simulated |
| 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 5340 # Number of instructions committed 35system.cpu.committedOps 5340 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 38system.cpu.num_func_calls 146 # number of times a function call or return occured 39system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls 40system.cpu.num_int_insts 4517 # number of integer instructions 41system.cpu.num_fp_insts 0 # number of float instructions 42system.cpu.num_int_register_reads 10620 # number of times the integer registers were read 43system.cpu.num_int_register_writes 4858 # number of times the integer registers were written 44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 46system.cpu.num_mem_refs 1402 # number of memory refs 47system.cpu.num_load_insts 724 # Number of load instructions 48system.cpu.num_store_insts 678 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles | 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 5340 # Number of instructions committed 35system.cpu.committedOps 5340 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 38system.cpu.num_func_calls 146 # number of times a function call or return occured 39system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls 40system.cpu.num_int_insts 4517 # number of integer instructions 41system.cpu.num_fp_insts 0 # number of float instructions 42system.cpu.num_int_register_reads 10620 # number of times the integer registers were read 43system.cpu.num_int_register_writes 4858 # number of times the integer registers were written 44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 46system.cpu.num_mem_refs 1402 # number of memory refs 47system.cpu.num_load_insts 724 # Number of load instructions 48system.cpu.num_store_insts 678 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 50system.cpu.num_busy_cycles 56412 # Number of busy cycles | 50system.cpu.num_busy_cycles 59082 # Number of busy cycles |
| 51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 0 # number of replacements | 51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 0 # number of replacements |
| 54system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use | 54system.cpu.icache.tagsinuse 117.079183 # Cycle average of tags in use |
| 55system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. 56system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. 57system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. 58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 55system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. 56system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. 57system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. 58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 59system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor 60system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy | 59system.cpu.icache.occ_blocks::cpu.inst 117.079183 # Average occupied blocks per requestor 60system.cpu.icache.occ_percent::cpu.inst 0.057168 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.057168 # Average percentage of cache occupancy |
| 62system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits 67system.cpu.icache.overall_hits::total 5127 # number of overall hits 68system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 0 # number of replacements | 62system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits 67system.cpu.icache.overall_hits::total 5127 # number of overall hits 68system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 0 # number of replacements |
| 132system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use | 132system.cpu.dcache.tagsinuse 82.107175 # Cycle average of tags in use |
| 133system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. 134system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. 135system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 133system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. 134system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. 135system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 137system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor 138system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy | 137system.cpu.dcache.occ_blocks::cpu.data 82.107175 # Average occupied blocks per requestor 138system.cpu.dcache.occ_percent::cpu.data 0.020046 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.020046 # Average percentage of cache occupancy |
| 140system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 142system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 144system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits 145system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits 146system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits 147system.cpu.dcache.overall_hits::total 1254 # number of overall hits --- 74 unchanged lines hidden (view full) --- 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 229system.cpu.l2cache.replacements 0 # number of replacements | 140system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits 142system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 144system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits 145system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits 146system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits 147system.cpu.dcache.overall_hits::total 1254 # number of overall hits --- 74 unchanged lines hidden (view full) --- 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 229system.cpu.l2cache.replacements 0 # number of replacements |
| 230system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use | 230system.cpu.l2cache.tagsinuse 142.223187 # Cycle average of tags in use |
| 231system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 232system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. 233system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. 234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 231system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 232system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. 233system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. 234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 235system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor 236system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor 237system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy 238system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy 239system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy | 235system.cpu.l2cache.occ_blocks::cpu.inst 116.548564 # Average occupied blocks per requestor 236system.cpu.l2cache.occ_blocks::cpu.data 25.674623 # Average occupied blocks per requestor 237system.cpu.l2cache.occ_percent::cpu.inst 0.003557 # Average percentage of cache occupancy 238system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy 239system.cpu.l2cache.occ_percent::total 0.004340 # Average percentage of cache occupancy |
| 240system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 241system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 242system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 243system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 244system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 245system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 246system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 247system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 111 unchanged lines hidden --- | 240system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 241system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 242system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 243system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 244system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 245system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 246system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 247system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits --- 111 unchanged lines hidden --- |