| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated |
| 4sim_ticks 30526500 # Number of ticks simulated 5final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 30915500 # Number of ticks simulated 5final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 232577 # Simulator instruction rate (inst/s) 8host_op_rate 232336 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1330299281 # Simulator tick rate (ticks/s) 10host_mem_usage 247080 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host | 7host_inst_rate 184246 # Simulator instruction rate (inst/s) 8host_op_rate 184150 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1068222426 # Simulator tick rate (ticks/s) 10host_mem_usage 250688 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 389 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 389 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 25system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 11 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 11 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 61053 # number of cpu cycles simulated | 36system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 61831 # number of cpu cycles simulated |
| 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 5327 # Number of instructions committed 41system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 44system.cpu.num_func_calls 146 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 46system.cpu.num_int_insts 4505 # number of integer instructions 47system.cpu.num_fp_insts 0 # number of float instructions 48system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 49system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 52system.cpu.num_mem_refs 1401 # number of memory refs 53system.cpu.num_load_insts 723 # Number of load instructions 54system.cpu.num_store_insts 678 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 5327 # Number of instructions committed 41system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 44system.cpu.num_func_calls 146 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 46system.cpu.num_int_insts 4505 # number of integer instructions 47system.cpu.num_fp_insts 0 # number of float instructions 48system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 49system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 52system.cpu.num_mem_refs 1401 # number of memory refs 53system.cpu.num_load_insts 723 # Number of load instructions 54system.cpu.num_store_insts 678 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 56system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles | 56system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles |
| 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 1121 # Number of branches fetched 60system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 61system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 64system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 90system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 91system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 5370 # Class of executed instruction | 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 1121 # Number of branches fetched 60system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 61system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 64system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 90system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 91system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 5370 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 96system.cpu.dcache.tags.replacements 0 # number of replacements | 96system.cpu.dcache.tags.replacements 0 # number of replacements |
| 97system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use | 97system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use |
| 98system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 98system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 102system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy | 102system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy |
| 105system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id 108system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 109system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 110system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses | 105system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id 108system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 109system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 110system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses |
| 111system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 111system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 112system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 113system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 114system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 116system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 117system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 118system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 119system.cpu.dcache.overall_hits::total 1253 # number of overall hits 120system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 121system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 122system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 123system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 124system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 125system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 126system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 127system.cpu.dcache.overall_misses::total 135 # number of overall misses | 112system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 113system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 114system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 116system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 117system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 118system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 119system.cpu.dcache.overall_hits::total 1253 # number of overall hits 120system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 121system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 122system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 123system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 124system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 125system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 126system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 127system.cpu.dcache.overall_misses::total 135 # number of overall misses |
| 128system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles 129system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles 130system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles 132system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles 133system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles 134system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles 135system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles | 128system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles 129system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles 130system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles 132system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles 133system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles 134system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles 135system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles |
| 136system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 137system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 138system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 139system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 140system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 141system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 142system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 143system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 144system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 145system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 146system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 147system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 148system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 149system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 150system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 151system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses | 136system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 137system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 138system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 139system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 140system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 141system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 142system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 143system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 144system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 145system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 146system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 147system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 148system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 149system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 150system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 151system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses |
| 152system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency 153system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency 154system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 155system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 156system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency 157system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency 158system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency 159system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency | 152system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency 153system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency 154system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 155system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 156system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency 157system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency 158system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency 159system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency |
| 160system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 161system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 162system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 167system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 168system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 169system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 170system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 171system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 172system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 173system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses | 160system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 161system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 162system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 167system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 168system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 169system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 170system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 171system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 172system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 173system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses |
| 174system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles 175system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles 176system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles 177system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles 178system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles 179system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles 180system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles 181system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles | 174system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss cycles 175system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles 176system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles 177system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles 178system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles 179system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles 180system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles 181system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles |
| 182system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 183system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 184system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 185system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 186system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 187system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 188system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 189system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses | 182system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 183system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 184system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 185system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 186system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 187system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 188system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 189system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses |
| 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency 191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency 198system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61092.592593 # average ReadReq mshr miss latency 191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61092.592593 # average ReadReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency 198system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 199system.cpu.icache.tags.replacements 0 # number of replacements | 199system.cpu.icache.tags.replacements 0 # number of replacements |
| 200system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use | 200system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use |
| 201system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 201system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 205system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy | 205system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy |
| 208system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id | 208system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id |
| 209system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id | 209system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id |
| 211system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 212system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 213system.cpu.icache.tags.data_accesses 10999 # Number of data accesses | 211system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 212system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 213system.cpu.icache.tags.data_accesses 10999 # Number of data accesses |
| 214system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 214system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 215system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 216system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 217system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 218system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 219system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 220system.cpu.icache.overall_hits::total 5114 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 223system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 224system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 225system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 226system.cpu.icache.overall_misses::total 257 # number of overall misses | 215system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 216system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 217system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 218system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 219system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 220system.cpu.icache.overall_hits::total 5114 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 223system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 224system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 225system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 226system.cpu.icache.overall_misses::total 257 # number of overall misses |
| 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles 228system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles 229system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles 231system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles 232system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles | 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles 228system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles 229system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles 231system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles 232system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles |
| 233system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 236system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 237system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 238system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 240system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 241system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 242system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 243system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 244system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses | 233system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 236system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 237system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 238system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 240system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 241system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 242system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 243system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 244system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses |
| 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency 246system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency 247system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency 248system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency | 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62620.622568 # average ReadReq miss latency 246system.cpu.icache.ReadReq_avg_miss_latency::total 62620.622568 # average ReadReq miss latency 247system.cpu.icache.demand_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency 248system.cpu.icache.demand_avg_miss_latency::total 62620.622568 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 62620.622568 # average overall miss latency |
| 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 258system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 259system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 260system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 261system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 262system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses | 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 258system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 259system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 260system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 261system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 262system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses |
| 263system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles 264system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles 266system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles 267system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles 268system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles | 263system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles 264system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles 266system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles 267system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles 268system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles |
| 269system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 270system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 271system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 272system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 273system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 274system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses | 269system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 270system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 271system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 272system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 273system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 274system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses |
| 275system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency 277system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency 279system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency 281system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 275system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.622568 # average ReadReq mshr miss latency 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61620.622568 # average ReadReq mshr miss latency 277system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency 279system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency 281system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 282system.cpu.l2cache.tags.replacements 0 # number of replacements | 282system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 283system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use | 283system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use |
| 284system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. | 284system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. |
| 285system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 286system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. | 285system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. 286system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. |
| 287system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 287system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 288system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor 289system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 296system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id | 288system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor 289system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id 294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id 296system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id |
| 297system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 298system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses | 297system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 298system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses |
| 299system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 299system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 300system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 301system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 302system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 303system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 304system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 305system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 306system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 307system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 6 unchanged lines hidden (view full) --- 314system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses 315system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses 316system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 317system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 318system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 319system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 320system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 321system.cpu.l2cache.overall_misses::total 389 # number of overall misses | 300system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 301system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 302system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 303system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 304system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 305system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 306system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 307system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 6 unchanged lines hidden (view full) --- 314system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses 315system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses 316system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 317system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 318system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 319system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 320system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 321system.cpu.l2cache.overall_misses::total 389 # number of overall misses |
| 322system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles 323system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles 324system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles 325system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles 326system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles 327system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles 328system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles 329system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles 330system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles 332system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles 333system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles | 322system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4900500 # number of ReadExReq miss cycles 323system.cpu.l2cache.ReadExReq_miss_latency::total 4900500 # number of ReadExReq miss cycles 324system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15428000 # number of ReadCleanReq miss cycles 325system.cpu.l2cache.ReadCleanReq_miss_latency::total 15428000 # number of ReadCleanReq miss cycles 326system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles 327system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles 328system.cpu.l2cache.demand_miss_latency::cpu.inst 15428000 # number of demand (read+write) miss cycles 329system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles 330system.cpu.l2cache.demand_miss_latency::total 23535000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.overall_miss_latency::cpu.inst 15428000 # number of overall miss cycles 332system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles 333system.cpu.l2cache.overall_miss_latency::total 23535000 # number of overall miss cycles |
| 334system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 335system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 336system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) 337system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses) 338system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses) 339system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses) 340system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 341system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 350system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses 351system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses 352system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 353system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 354system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 355system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 356system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 357system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses | 334system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 335system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 336system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) 337system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses) 338system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses) 339system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses) 340system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 341system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 350system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses 351system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses 352system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 353system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 354system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 355system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 356system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 357system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses |
| 358system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 359system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 360system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency 361system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency 362system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 363system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 364system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency 367system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency | 358system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 359system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 360system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency 361system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency 362system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 363system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 364system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency 367system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency |
| 370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 377system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 378system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses 379system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses 380system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 381system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 382system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 383system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 384system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 386system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 387system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses | 370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 377system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 378system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses 379system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses 380system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 381system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 382system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 383system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 384system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 386system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 387system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses |
| 388system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles 389system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles 390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles 391system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles 392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles 393system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles 398system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles | 388system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles 389system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles 390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles 391system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles 392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles 393system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles 398system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles |
| 400system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses 405system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses 406system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 407system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 408system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 409system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 410system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 411system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses | 400system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses 405system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses 406system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 407system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 408system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 409system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 410system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 411system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses |
| 412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 413system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency 415system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency | 412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 413system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency 415system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency |
| 424system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 424system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 430system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 430system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 431system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution 436system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 450system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 455system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 456system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) | 431system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution 436system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 450system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 455system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 456system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) |
| 458system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) | 458system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) |
| 459system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 459system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 461system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states | 461system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. 462system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 463system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 465system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 466system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 467system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states |
| 462system.membus.trans_dist::ReadResp 308 # Transaction distribution 463system.membus.trans_dist::ReadExReq 81 # Transaction distribution 464system.membus.trans_dist::ReadExResp 81 # Transaction distribution 465system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 466system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 467system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 468system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 469system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 477system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 478system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 479system.membus.snoop_fanout::min_value 0 # Request fanout histogram 480system.membus.snoop_fanout::max_value 0 # Request fanout histogram 481system.membus.snoop_fanout::total 389 # Request fanout histogram 482system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) 483system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 484system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) | 468system.membus.trans_dist::ReadResp 308 # Transaction distribution 469system.membus.trans_dist::ReadExReq 81 # Transaction distribution 470system.membus.trans_dist::ReadExResp 81 # Transaction distribution 471system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 473system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 474system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 475system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 483system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 484system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 485system.membus.snoop_fanout::min_value 0 # Request fanout histogram 486system.membus.snoop_fanout::max_value 0 # Request fanout histogram 487system.membus.snoop_fanout::total 389 # Request fanout histogram 488system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) 489system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 490system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) |
| 485system.membus.respLayer1.utilization 6.4 # Layer utilization (%) | 491system.membus.respLayer1.utilization 6.3 # Layer utilization (%) |
| 486 487---------- End Simulation Statistics ---------- | 492 493---------- End Simulation Statistics ---------- |