| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30526500 # Number of ticks simulated 5final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30526500 # Number of ticks simulated 5final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 398653 # Simulator instruction rate (inst/s) 8host_op_rate 397863 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2276293986 # Simulator tick rate (ticks/s) 10host_mem_usage 245124 # Number of bytes of host memory used | 7host_inst_rate 412582 # Simulator instruction rate (inst/s) 8host_op_rate 412293 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2361216779 # Simulator tick rate (ticks/s) 10host_mem_usage 290052 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 11 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 11 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.numCycles 61053 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 5327 # Number of instructions committed 38system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 41system.cpu.num_func_calls 146 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 84system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 87system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 88system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 5370 # Class of executed instruction | 37system.cpu.numCycles 61053 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 5327 # Number of instructions committed 41system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 44system.cpu.num_func_calls 146 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 90system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 91system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 5370 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 92system.cpu.dcache.tags.replacements 0 # number of replacements 93system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id 104system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 105system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 106system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses | 96system.cpu.dcache.tags.replacements 0 # number of replacements 97system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id 108system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 109system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 110system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses |
| 111system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 107system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 108system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 109system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 110system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 111system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 112system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 113system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 114system.cpu.dcache.overall_hits::total 1253 # number of overall hits --- 70 unchanged lines hidden (view full) --- 185system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency 186system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency 187system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 188system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 189system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 190system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency 191system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 192system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency | 112system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 113system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 114system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 116system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 117system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 118system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 119system.cpu.dcache.overall_hits::total 1253 # number of overall hits --- 70 unchanged lines hidden (view full) --- 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency 191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency |
| 198system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 193system.cpu.icache.tags.replacements 0 # number of replacements 194system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use 195system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 196system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 197system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 198system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor 200system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy 201system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy 202system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 203system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 204system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 205system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 206system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 207system.cpu.icache.tags.data_accesses 10999 # Number of data accesses | 199system.cpu.icache.tags.replacements 0 # number of replacements 200system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use 201system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 205system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy 208system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 209system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 211system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 212system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 213system.cpu.icache.tags.data_accesses 10999 # Number of data accesses |
| 214system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 208system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 209system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 210system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 211system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 212system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 213system.cpu.icache.overall_hits::total 5114 # number of overall hits 214system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 215system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 266system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 267system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 268system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency 269system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency 270system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 271system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency 272system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 273system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency | 215system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 216system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 217system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 218system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 219system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 220system.cpu.icache.overall_hits::total 5114 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 273system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 274system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 275system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency 277system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency 279system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency |
| 281system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 274system.cpu.l2cache.tags.replacements 0 # number of replacements 275system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use 276system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 277system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 278system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 279system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 280system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor 281system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor 282system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy 283system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy 284system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy 285system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 286system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 287system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 288system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 289system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 290system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses | 282system.cpu.l2cache.tags.replacements 0 # number of replacements 283system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use 284system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 285system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 286system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 287system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 288system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor 289system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 296system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 297system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 298system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses |
| 299system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 291system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 292system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 293system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 294system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 295system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 296system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 297system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 298system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 114 unchanged lines hidden (view full) --- 413system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 414system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency 415system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. 416system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. 417system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 418system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 419system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 420system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 300system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 301system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 302system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 303system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 304system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 305system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 306system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 307system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 114 unchanged lines hidden (view full) --- 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency 424system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 430system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
|
| 421system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 422system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 423system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution 426system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 427system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 428system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 442system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 443system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 444system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 445system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 446system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 447system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 448system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 449system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 431system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution 436system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 452system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 454system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 455system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 456system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 457system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 460system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states |
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| 450system.membus.trans_dist::ReadResp 308 # Transaction distribution 451system.membus.trans_dist::ReadExReq 81 # Transaction distribution 452system.membus.trans_dist::ReadExResp 81 # Transaction distribution 453system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 454system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 455system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 456system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 457system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 461system.membus.trans_dist::ReadResp 308 # Transaction distribution 462system.membus.trans_dist::ReadExReq 81 # Transaction distribution 463system.membus.trans_dist::ReadExResp 81 # Transaction distribution 464system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 465system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 466system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 467system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 468system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |