| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28206000 # Number of ticks simulated 5final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 427855 # Simulator instruction rate (inst/s) 8host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2253599179 # Simulator tick rate (ticks/s) 10host_mem_usage 221156 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 5340 # Number of instructions simulated 13sim_ops 5340 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.workload.num_syscalls 11 # Number of system calls 31system.cpu.numCycles 56412 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 5340 # Number of instructions committed 35system.cpu.committedOps 5340 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 79system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles 80system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses) 81system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses) 82system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses 83system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses 84system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses 85system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses 86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses |
| 87system.cpu.icache.ReadReq_miss_rate::total 0.047734 # miss rate for ReadReq accesses |
| 88system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses |
| 89system.cpu.icache.demand_miss_rate::total 0.047734 # miss rate for demand accesses |
| 90system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses |
| 91system.cpu.icache.overall_miss_rate::total 0.047734 # miss rate for overall accesses |
| 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency |
| 93system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency |
| 94system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency |
| 95system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency |
| 96system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency |
| 97system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency |
| 98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104system.cpu.icache.fast_writes 0 # number of fast writes performed 105system.cpu.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 111system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses 112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles 113system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles 114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles 115system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles 116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles 117system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles 118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses |
| 119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047734 # mshr miss rate for ReadReq accesses |
| 120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses |
| 121system.cpu.icache.demand_mshr_miss_rate::total 0.047734 # mshr miss rate for demand accesses |
| 122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses |
| 123system.cpu.icache.overall_mshr_miss_rate::total 0.047734 # mshr miss rate for overall accesses |
| 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency |
| 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency |
| 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency |
| 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency |
| 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency |
| 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency |
| 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 0 # number of replacements 132system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use 133system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. 134system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. 135system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 137system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 165system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) 166system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 167system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 168system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses 169system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses 170system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses 171system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses 172system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses |
| 173system.cpu.dcache.ReadReq_miss_rate::total 0.075419 # miss rate for ReadReq accesses |
| 174system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses |
| 175system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses |
| 176system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses |
| 177system.cpu.dcache.demand_miss_rate::total 0.097192 # miss rate for demand accesses |
| 178system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses |
| 179system.cpu.dcache.overall_miss_rate::total 0.097192 # miss rate for overall accesses |
| 180system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency |
| 181system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency |
| 182system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency |
| 183system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency |
| 184system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency |
| 185system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency |
| 186system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency |
| 187system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency |
| 188system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 189system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 190system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 191system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 192system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 193system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194system.cpu.dcache.fast_writes 0 # number of fast writes performed 195system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 205system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles 206system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles 207system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles 208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles 209system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles 210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles 211system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles 212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses |
| 213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses |
| 214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses |
| 215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses |
| 216system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses |
| 217system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses |
| 218system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses |
| 219system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses |
| 220system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency |
| 221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency |
| 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency |
| 223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency |
| 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency |
| 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency |
| 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency |
| 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency |
| 228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 229system.cpu.l2cache.replacements 0 # number of replacements 230system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use 231system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 232system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. 233system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. 234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 235system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor --- 40 unchanged lines hidden (view full) --- 276system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 277system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 278system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses 279system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses 280system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 281system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses 282system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses 283system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses |
| 284system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses |
| 285system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 286system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 287system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 288system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses |
| 289system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses |
| 290system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 291system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses |
| 292system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses |
| 293system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency |
| 295system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency |
| 296system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency |
| 297system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency |
| 298system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 299system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency |
| 300system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency |
| 301system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 302system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency |
| 303system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency |
| 304system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 305system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 306system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 307system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 308system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 309system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 310system.cpu.l2cache.fast_writes 0 # number of fast writes performed 311system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 328system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles 329system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 330system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles 331system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles 332system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 333system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles 334system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses 335system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses |
| 336system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses |
| 337system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 338system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 339system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 340system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses |
| 341system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses |
| 342system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 343system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses |
| 344system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses |
| 345system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 346system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency |
| 347system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |
| 348system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency |
| 349system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency |
| 350system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 351system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 352system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
| 353system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 354system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 355system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
| 356system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 357 358---------- End Simulation Statistics ---------- |