4,5c4,5
< sim_ticks 30526500 # Number of ticks simulated
< final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30915500 # Number of ticks simulated
> final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 232577 # Simulator instruction rate (inst/s)
< host_op_rate 232336 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1330299281 # Simulator tick rate (ticks/s)
< host_mem_usage 247080 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 184246 # Simulator instruction rate (inst/s)
> host_op_rate 184150 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1068222426 # Simulator tick rate (ticks/s)
> host_mem_usage 250688 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 61053 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 61831 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy
111c111
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
128,135c128,135
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles
152,159c152,159
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency
174,181c174,181
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles
190,198c190,198
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61092.592593 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61092.592593 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
200c200
< system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use
205,207c205,207
< system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy
209,210c209,210
< system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
214c214
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
227,232c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles
245,250c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62620.622568 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62620.622568 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62620.622568 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62620.622568 # average overall miss latency
263,268c263,268
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles
275,281c275,281
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.622568 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61620.622568 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
283c283
< system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use
285,286c285,286
< system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks.
288,296c288,296
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id
299c299
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
322,333c322,333
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15428000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 15428000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15428000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23535000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15428000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23535000 # number of overall miss cycles
358,369c358,369
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency
388,399c388,399
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles
412,423c412,423
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency
430c430
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
458c458
< system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
461c461,467
< system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
485c491
< system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
< sim_ticks 30526500 # Number of ticks simulated
< final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30915500 # Number of ticks simulated
> final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 232577 # Simulator instruction rate (inst/s)
< host_op_rate 232336 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1330299281 # Simulator tick rate (ticks/s)
< host_mem_usage 247080 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 184246 # Simulator instruction rate (inst/s)
> host_op_rate 184150 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1068222426 # Simulator tick rate (ticks/s)
> host_mem_usage 250688 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 61053 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 61831 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy
111c111
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
128,135c128,135
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles
152,159c152,159
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency
174,181c174,181
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles
190,198c190,198
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61092.592593 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61092.592593 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
200c200
< system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use
205,207c205,207
< system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy
209,210c209,210
< system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
214c214
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
227,232c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles
245,250c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62620.622568 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62620.622568 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62620.622568 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62620.622568 # average overall miss latency
263,268c263,268
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles
275,281c275,281
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.622568 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61620.622568 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
283c283
< system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use
285,286c285,286
< system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks.
288,296c288,296
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id
299c299
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
322,333c322,333
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15428000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 15428000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15428000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23535000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15428000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23535000 # number of overall miss cycles
358,369c358,369
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency
388,399c388,399
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles
412,423c412,423
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency
430c430
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
458c458
< system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
461c461,467
< system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states
485c491
< system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 6.3 # Layer utilization (%)