4,5c4,5
< sim_ticks 27800500 # Number of ticks simulated
< final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27803500 # Number of ticks simulated
> final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 428112 # Simulator instruction rate (inst/s)
< host_op_rate 427631 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2229390537 # Simulator tick rate (ticks/s)
< host_mem_usage 290104 # Number of bytes of host memory used
---
> host_inst_rate 506128 # Simulator instruction rate (inst/s)
> host_op_rate 505504 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2635153066 # Simulator tick rate (ticks/s)
> host_mem_usage 292480 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s)
34c34
< system.cpu.numCycles 55601 # number of cpu cycles simulated
---
> system.cpu.numCycles 55607 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use
98c98
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor
123,124c123,124
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles
127,130c127,130
< system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles
147,148c147,148
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency
151,154c151,154
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency
171,172c171,172
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles
175,178c175,178
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles
187,188c187,188
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency
191,194c191,194
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
197c197
< system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use
202,204c202,204
< system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy
223,228c223,228
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles
241,246c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency
261,266c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles
273,278c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
281c281
< system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use
286,287c286,287
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor
423a424,429
> system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
437,438c443,444
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram
440,441c446,447
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram
444c450
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 27800500 # Number of ticks simulated
< final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27803500 # Number of ticks simulated
> final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 428112 # Simulator instruction rate (inst/s)
< host_op_rate 427631 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2229390537 # Simulator tick rate (ticks/s)
< host_mem_usage 290104 # Number of bytes of host memory used
---
> host_inst_rate 506128 # Simulator instruction rate (inst/s)
> host_op_rate 505504 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2635153066 # Simulator tick rate (ticks/s)
> host_mem_usage 292480 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s)
34c34
< system.cpu.numCycles 55601 # number of cpu cycles simulated
---
> system.cpu.numCycles 55607 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use
98c98
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor
123,124c123,124
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles
127,130c127,130
< system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles
147,148c147,148
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency
151,154c151,154
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency
171,172c171,172
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles
175,178c175,178
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles
187,188c187,188
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency
191,194c191,194
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
197c197
< system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use
202,204c202,204
< system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy
223,228c223,228
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles
241,246c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency
261,266c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles
273,278c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
281c281
< system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use
286,287c286,287
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor
423a424,429
> system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
437,438c443,444
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram
440,441c446,447
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram
444c450
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram