4,5c4,5
< sim_ticks 27800000 # Number of ticks simulated
< final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27800500 # Number of ticks simulated
> final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 583909 # Simulator instruction rate (inst/s)
< host_op_rate 583078 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3038583452 # Simulator tick rate (ticks/s)
< host_mem_usage 285748 # Number of bytes of host memory used
---
> host_inst_rate 510787 # Simulator instruction rate (inst/s)
> host_op_rate 510102 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2658808340 # Simulator tick rate (ticks/s)
> host_mem_usage 289420 # Number of bytes of host memory used
24,54c24,31
< system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 308 # Transaction distribution
< system.membus.trans_dist::ReadResp 308 # Transaction distribution
< system.membus.trans_dist::ReadExReq 81 # Transaction distribution
< system.membus.trans_dist::ReadExResp 81 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 389 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 389 # Request fanout histogram
< system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.6 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
57c34
< system.cpu.numCycles 55600 # number of cpu cycles simulated
---
> system.cpu.numCycles 55601 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
114a92,195
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
> system.cpu.dcache.overall_hits::total 1253 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
> system.cpu.dcache.overall_misses::total 135 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c197
< system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use
121,123c202,204
< system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy
142,147c223,228
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
160,165c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
180,185c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles
192,197c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
200c281
< system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use
205,206c286,287
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor
236,246c317,327
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
269,279c350,360
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
299,309c380,390
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles
321,331c402,412
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
333,436d413
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
< system.cpu.dcache.overall_hits::total 1253 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
< system.cpu.dcache.overall_misses::total 135 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
464a442,464
> system.membus.trans_dist::ReadReq 308 # Transaction distribution
> system.membus.trans_dist::ReadResp 308 # Transaction distribution
> system.membus.trans_dist::ReadExReq 81 # Transaction distribution
> system.membus.trans_dist::ReadExResp 81 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 389 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 389 # Request fanout histogram
> system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
< sim_ticks 27800000 # Number of ticks simulated
< final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27800500 # Number of ticks simulated
> final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 583909 # Simulator instruction rate (inst/s)
< host_op_rate 583078 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3038583452 # Simulator tick rate (ticks/s)
< host_mem_usage 285748 # Number of bytes of host memory used
---
> host_inst_rate 510787 # Simulator instruction rate (inst/s)
> host_op_rate 510102 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2658808340 # Simulator tick rate (ticks/s)
> host_mem_usage 289420 # Number of bytes of host memory used
24,54c24,31
< system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 308 # Transaction distribution
< system.membus.trans_dist::ReadResp 308 # Transaction distribution
< system.membus.trans_dist::ReadExReq 81 # Transaction distribution
< system.membus.trans_dist::ReadExResp 81 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 389 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 389 # Request fanout histogram
< system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.6 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
57c34
< system.cpu.numCycles 55600 # number of cpu cycles simulated
---
> system.cpu.numCycles 55601 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
114a92,195
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
> system.cpu.dcache.overall_hits::total 1253 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
> system.cpu.dcache.overall_misses::total 135 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c197
< system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use
121,123c202,204
< system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy
142,147c223,228
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
160,165c241,246
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
180,185c261,266
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles
192,197c273,278
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
200c281
< system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use
205,206c286,287
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor
236,246c317,327
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
269,279c350,360
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
299,309c380,390
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles
321,331c402,412
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
333,436d413
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
< system.cpu.dcache.overall_hits::total 1253 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
< system.cpu.dcache.overall_misses::total 135 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
464a442,464
> system.membus.trans_dist::ReadReq 308 # Transaction distribution
> system.membus.trans_dist::ReadResp 308 # Transaction distribution
> system.membus.trans_dist::ReadExReq 81 # Transaction distribution
> system.membus.trans_dist::ReadExResp 81 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 389 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 389 # Request fanout histogram
> system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.0 # Layer utilization (%)