1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28206000 # Number of ticks simulated
5final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28206000 # Number of ticks simulated
5final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 240215 # Simulator instruction rate (inst/s)
8host_op_rate 240049 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1267195715 # Simulator tick rate (ticks/s)
10host_mem_usage 220748 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
| 7host_inst_rate 427855 # Simulator instruction rate (inst/s)
8host_op_rate 427237 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2253599179 # Simulator tick rate (ticks/s)
10host_mem_usage 221156 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
|
12sim_insts 5340 # Number of instructions simulated
13sim_ops 5340 # Number of ops (including micro ops) simulated
| 12sim_insts 5340 # Number of instructions simulated
13sim_ops 5340 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 24896 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 389 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 882649082 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 578600298 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 882649082 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
16system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s)
|
23system.cpu.workload.num_syscalls 11 # Number of system calls
24system.cpu.numCycles 56412 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.committedInsts 5340 # Number of instructions committed
28system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
29system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
30system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
31system.cpu.num_func_calls 146 # number of times a function call or return occured
32system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls
33system.cpu.num_int_insts 4517 # number of integer instructions
34system.cpu.num_fp_insts 0 # number of float instructions
35system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
36system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
37system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
38system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
39system.cpu.num_mem_refs 1402 # number of memory refs
40system.cpu.num_load_insts 724 # Number of load instructions
41system.cpu.num_store_insts 678 # Number of store instructions
42system.cpu.num_idle_cycles 0 # Number of idle cycles
43system.cpu.num_busy_cycles 56412 # Number of busy cycles
44system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45system.cpu.idle_fraction 0 # Percentage of idle cycles
46system.cpu.icache.replacements 0 # number of replacements
47system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use
48system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
49system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
50system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
51system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor
53system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy
54system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy
55system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits
56system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits
57system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits
58system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits
59system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits
60system.cpu.icache.overall_hits::total 5127 # number of overall hits
61system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
62system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
63system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
64system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
65system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
66system.cpu.icache.overall_misses::total 257 # number of overall misses
67system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles
68system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles
69system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles
70system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles
71system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles
72system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles
73system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses)
74system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses
76system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses
77system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses
78system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses
79system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses
| 30system.cpu.workload.num_syscalls 11 # Number of system calls
31system.cpu.numCycles 56412 # number of cpu cycles simulated
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34system.cpu.committedInsts 5340 # Number of instructions committed
35system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
36system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
38system.cpu.num_func_calls 146 # number of times a function call or return occured
39system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls
40system.cpu.num_int_insts 4517 # number of integer instructions
41system.cpu.num_fp_insts 0 # number of float instructions
42system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
43system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
46system.cpu.num_mem_refs 1402 # number of memory refs
47system.cpu.num_load_insts 724 # Number of load instructions
48system.cpu.num_store_insts 678 # Number of store instructions
49system.cpu.num_idle_cycles 0 # Number of idle cycles
50system.cpu.num_busy_cycles 56412 # Number of busy cycles
51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
52system.cpu.idle_fraction 0 # Percentage of idle cycles
53system.cpu.icache.replacements 0 # number of replacements
54system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use
55system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
56system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
57system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor
60system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy
61system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy
62system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits
63system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits
64system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits
65system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits
66system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits
67system.cpu.icache.overall_hits::total 5127 # number of overall hits
68system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
69system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
70system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
71system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
72system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
73system.cpu.icache.overall_misses::total 257 # number of overall misses
74system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles
75system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles
76system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles
77system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles
78system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles
79system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles
80system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses)
81system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses)
82system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses
83system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses
84system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses
85system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses
86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses
|
| 87system.cpu.icache.ReadReq_miss_rate::total 0.047734 # miss rate for ReadReq accesses
|
80system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses
| 88system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses
|
| 89system.cpu.icache.demand_miss_rate::total 0.047734 # miss rate for demand accesses
|
81system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses
| 90system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses
|
| 91system.cpu.icache.overall_miss_rate::total 0.047734 # miss rate for overall accesses
|
82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency
| 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency
|
| 93system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency
|
83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
| 94system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
|
| 95system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency
|
84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
| 96system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
|
| 97system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency
|
85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
89system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
90system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
91system.cpu.icache.fast_writes 0 # number of fast writes performed
92system.cpu.icache.cache_copies 0 # number of cache copies performed
93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
94system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
95system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
96system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
97system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
98system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
99system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles
100system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
105system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses
| 98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
104system.cpu.icache.fast_writes 0 # number of fast writes performed
105system.cpu.icache.cache_copies 0 # number of cache copies performed
106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
107system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
108system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
109system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
110system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
111system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles
113system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles
114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles
115system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
117system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses
|
| 119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047734 # mshr miss rate for ReadReq accesses
|
106system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses
| 120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses
|
| 121system.cpu.icache.demand_mshr_miss_rate::total 0.047734 # mshr miss rate for demand accesses
|
107system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses
| 122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses
|
| 123system.cpu.icache.overall_mshr_miss_rate::total 0.047734 # mshr miss rate for overall accesses
|
108system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
| 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
|
| 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency
|
109system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
| 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
|
| 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
|
110system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
| 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
|
| 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
|
111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112system.cpu.dcache.replacements 0 # number of replacements
113system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use
114system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
115system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
116system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
117system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor
119system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy
120system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy
121system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits
122system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits
123system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
124system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
125system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits
126system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits
127system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits
128system.cpu.dcache.overall_hits::total 1254 # number of overall hits
129system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
130system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
131system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
132system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
133system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
134system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
135system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
136system.cpu.dcache.overall_misses::total 135 # number of overall misses
137system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles
138system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles
139system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles
140system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles
141system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles
142system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles
143system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles
144system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles
145system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
149system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses
150system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses
151system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses
152system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses
153system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses
| 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131system.cpu.dcache.replacements 0 # number of replacements
132system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use
133system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
134system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
135system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
137system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor
138system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy
139system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy
140system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits
141system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits
142system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
143system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
144system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits
145system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits
146system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits
147system.cpu.dcache.overall_hits::total 1254 # number of overall hits
148system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
149system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
150system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
151system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
152system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
153system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
154system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
155system.cpu.dcache.overall_misses::total 135 # number of overall misses
156system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles
157system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles
158system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles
159system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles
160system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles
161system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles
162system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles
163system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles
164system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses)
165system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses)
166system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
167system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
168system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses
169system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses
170system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses
171system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses
172system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses
|
| 173system.cpu.dcache.ReadReq_miss_rate::total 0.075419 # miss rate for ReadReq accesses
|
154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
| 174system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
|
| 175system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
|
155system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses
| 176system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses
|
| 177system.cpu.dcache.demand_miss_rate::total 0.097192 # miss rate for demand accesses
|
156system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses
| 178system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses
|
| 179system.cpu.dcache.overall_miss_rate::total 0.097192 # miss rate for overall accesses
|
157system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency
| 180system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency
|
| 181system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency
|
158system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
| 182system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
| 183system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
159system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
| 184system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
|
| 185system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency
|
160system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
| 186system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
|
| 187system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency
|
161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
167system.cpu.dcache.fast_writes 0 # number of fast writes performed
168system.cpu.dcache.cache_copies 0 # number of cache copies performed
169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
170system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
172system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
173system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
174system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
175system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
176system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
177system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
178system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
179system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
180system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
181system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
182system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
183system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
184system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
185system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses
| 188system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
189system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
190system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
191system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
192system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
193system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
194system.cpu.dcache.fast_writes 0 # number of fast writes performed
195system.cpu.dcache.cache_copies 0 # number of cache copies performed
196system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
197system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
198system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
199system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
200system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
201system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
202system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
203system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
204system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
206system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
207system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
209system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
211system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses
|
| 213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses
|
186system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
| 214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
| 215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses
| 216system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses
|
| 217system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses
|
188system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses
| 218system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses
|
| 219system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses
|
189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
| 220system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
|
| 221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
|
190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
| 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
| 223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
| 224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
|
| 225system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
|
192system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
| 226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
|
| 227system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
|
193system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
194system.cpu.l2cache.replacements 0 # number of replacements
195system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use
196system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
197system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
198system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
199system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor
201system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor
202system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy
203system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
204system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy
205system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
206system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
207system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
208system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
209system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
210system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
211system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
212system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
213system.cpu.l2cache.overall_hits::total 3 # number of overall hits
214system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses
215system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
216system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses
217system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
218system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
219system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
220system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
221system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
222system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
223system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
224system.cpu.l2cache.overall_misses::total 389 # number of overall misses
225system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles
226system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
227system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles
228system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles
229system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles
230system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles
231system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
232system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles
233system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles
234system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
235system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles
236system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses)
237system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
238system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses)
239system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
240system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
241system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
242system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
243system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
244system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses
245system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
246system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses
247system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses
248system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
| 228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
229system.cpu.l2cache.replacements 0 # number of replacements
230system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use
231system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
232system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
233system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
235system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor
236system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor
237system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy
238system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
239system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy
240system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
241system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
242system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
243system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
244system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
245system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
246system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
247system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
248system.cpu.l2cache.overall_hits::total 3 # number of overall hits
249system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses
250system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
251system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses
252system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
253system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
254system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
255system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
256system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
257system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
258system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
259system.cpu.l2cache.overall_misses::total 389 # number of overall misses
260system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles
261system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
262system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles
263system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles
264system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles
265system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles
266system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
267system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles
268system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles
269system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
270system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles
271system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses)
272system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
273system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses)
274system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
275system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
276system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
277system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
278system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
279system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses
280system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
281system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses
282system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses
283system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
| 284system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses
|
249system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
| 285system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
| 286system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
250system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
251system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
| 287system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
288system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
| 289system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
|
252system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
253system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
| 290system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
291system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
| 292system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
|
254system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
255system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
| 293system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
| 295system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
256system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
| 296system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
| 297system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
257system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
258system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
| 298system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
299system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
| 300system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
259system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
260system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
| 301system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
302system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
| 303system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
261system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
262system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
263system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
264system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
265system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
266system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
267system.cpu.l2cache.fast_writes 0 # number of fast writes performed
268system.cpu.l2cache.cache_copies 0 # number of cache copies performed
269system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses
270system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
271system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses
272system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
273system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
274system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
275system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
276system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
277system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
278system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
279system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
280system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
281system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
282system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
283system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
284system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
285system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
286system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
287system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
288system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
289system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
290system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
291system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
292system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
| 304system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
305system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
306system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
307system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
308system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
309system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
310system.cpu.l2cache.fast_writes 0 # number of fast writes performed
311system.cpu.l2cache.cache_copies 0 # number of cache copies performed
312system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses
313system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
314system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses
315system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
316system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
317system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
318system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
319system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
320system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
321system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
322system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
323system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
324system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
325system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
326system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
327system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
328system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
329system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
330system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
331system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
332system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
333system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
334system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
335system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
| 336system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses
|
293system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
| 337system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
| 338system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
294system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
295system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
| 339system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
340system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
| 341system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
|
296system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
297system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
| 342system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
343system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
| 344system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
|
298system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
299system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
| 345system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
346system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
| 347system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
300system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
| 348system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
| 349system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
301system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
| 350system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
351system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
| 352system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
303system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
304system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
| 353system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
354system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
| 355system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
305system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
306
307---------- End Simulation Statistics ----------
| 356system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
357
358---------- End Simulation Statistics ----------
|