Cross Reference: /gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt

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stats.txt (10063:9595c7a1d837)	stats.txt (10220:9eab5efc02e8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27800000 # Number of ticks simulated 5final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27800000 # Number of ticks simulated 5final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 49661 # Simulator instruction rate (inst/s) 8host_op_rate 49653 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 259077754 # Simulator tick rate (ticks/s) 10host_mem_usage 284248 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host	7host_inst_rate 487107 # Simulator instruction rate (inst/s) 8host_op_rate 486440 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2535570960 # Simulator tick rate (ticks/s) 10host_mem_usage 269788 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 895539568 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 308 # Transaction distribution 34system.membus.trans_dist::ReadResp 308 # Transaction distribution 35system.membus.trans_dist::ReadExReq 81 # Transaction distribution 36system.membus.trans_dist::ReadExResp 81 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 24896 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 45system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 12.6 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 11 # Number of system calls 49system.cpu.numCycles 55600 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 5327 # Number of instructions committed 53system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 56system.cpu.num_func_calls 146 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 58system.cpu.num_int_insts 4505 # number of integer instructions 59system.cpu.num_fp_insts 0 # number of float instructions 60system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 61system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 64system.cpu.num_mem_refs 1401 # number of memory refs 65system.cpu.num_load_insts 723 # Number of load instructions 66system.cpu.num_store_insts 678 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 55600 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.Branches 1121 # Number of branches fetched	12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 895539568 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 308 # Transaction distribution 34system.membus.trans_dist::ReadResp 308 # Transaction distribution 35system.membus.trans_dist::ReadExReq 81 # Transaction distribution 36system.membus.trans_dist::ReadExResp 81 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 24896 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 45system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 12.6 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 11 # Number of system calls 49system.cpu.numCycles 55600 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 5327 # Number of instructions committed 53system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 56system.cpu.num_func_calls 146 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 58system.cpu.num_int_insts 4505 # number of integer instructions 59system.cpu.num_fp_insts 0 # number of float instructions 60system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 61system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 64system.cpu.num_mem_refs 1401 # number of memory refs 65system.cpu.num_load_insts 723 # Number of load instructions 66system.cpu.num_store_insts 678 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 55600 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.Branches 1121 # Number of branches fetched
	72system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 73system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 74system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 75system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 76system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 77system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 78system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 79system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 80system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 81system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 82system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 83system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 84system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 85system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 86system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 87system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 88system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 89system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 90system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 91system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 92system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 93system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 94system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 95system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 96system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 97system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 98system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 99system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 100system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 101system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 102system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 103system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 104system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 105system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 106system.cpu.op_class::total 5370 # Class of executed instruction
72system.cpu.icache.tags.replacements 0 # number of replacements 73system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use 74system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 75system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 76system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 77system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor 79system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy 80system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy 81system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 82system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 83system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 84system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 85system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 86system.cpu.icache.tags.data_accesses 10999 # Number of data accesses 87system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 88system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 89system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 90system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 91system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 92system.cpu.icache.overall_hits::total 5114 # number of overall hits 93system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 94system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 95system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 96system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 97system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 98system.cpu.icache.overall_misses::total 257 # number of overall misses 99system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles 100system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles 101system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles 102system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles 103system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles 104system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles 105system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 106system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 107system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 108system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 109system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 110system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 111system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 112system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 113system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 114system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 115system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 116system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses 117system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency 118system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency 119system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 120system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency 121system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 122system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency 123system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 124system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 125system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 126system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 127system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 128system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 129system.cpu.icache.fast_writes 0 # number of fast writes performed 130system.cpu.icache.cache_copies 0 # number of cache copies performed 131system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 132system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 133system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 134system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 135system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 136system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses 137system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles 138system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles 139system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles 140system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles 141system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles 142system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles 143system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 144system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 145system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 146system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 147system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 148system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 149system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency 150system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency 151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 152system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 154system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 155system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 156system.cpu.l2cache.tags.replacements 0 # number of replacements 157system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use 158system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 159system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 160system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 161system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 162system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor 163system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor 164system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy 165system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy 166system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy 167system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 168system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 169system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 170system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 171system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 172system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses 173system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 174system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 175system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 176system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 177system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 178system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 179system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 180system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 181system.cpu.l2cache.overall_hits::total 3 # number of overall hits 182system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses 183system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 184system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses 185system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses 186system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses 187system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 188system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 189system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 190system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 191system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 192system.cpu.l2cache.overall_misses::total 389 # number of overall misses 193system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles 194system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles 195system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles 196system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles 197system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles 198system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles 199system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 200system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles 201system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles 202system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 203system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles 204system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) 205system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) 206system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) 207system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 208system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 209system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 210system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 211system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses 212system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses 213system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 214system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses 215system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses 216system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses 217system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses 218system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 219system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 220system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 221system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 222system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 223system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 224system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 225system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses 226system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 227system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 228system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 229system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 230system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 231system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 232system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 233system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 234system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 235system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 236system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 237system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 238system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 239system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 240system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 241system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 242system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 243system.cpu.l2cache.fast_writes 0 # number of fast writes performed 244system.cpu.l2cache.cache_copies 0 # number of cache copies performed 245system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses 246system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 247system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses 248system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 249system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 250system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 251system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 252system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 253system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 254system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 255system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses 256system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles 257system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles 258system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles 259system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles 260system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles 261system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles 262system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 263system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles 264system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles 265system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 266system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles 267system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses 268system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses 269system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses 270system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 271system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 272system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 273system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 274system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 275system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 276system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 277system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses 278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 281system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 283system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 285system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 286system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 287system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 288system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 289system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 290system.cpu.dcache.tags.replacements 0 # number of replacements 291system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use 292system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 293system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 294system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 295system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 296system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor 297system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy 298system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy 299system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 300system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 301system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 302system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 303system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 304system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses 305system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 306system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 307system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 308system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 309system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 310system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 311system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 312system.cpu.dcache.overall_hits::total 1253 # number of overall hits 313system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 314system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 315system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 316system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 317system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 318system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 319system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 320system.cpu.dcache.overall_misses::total 135 # number of overall misses 321system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles 322system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles 323system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles 324system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles 325system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles 326system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles 327system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles 328system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles 329system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 330system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 331system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 332system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 333system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 334system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 335system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 336system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 337system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 338system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 339system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 340system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 341system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 342system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 343system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 344system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency 346system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency 347system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 348system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 349system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 350system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency 351system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 352system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency 353system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 354system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 355system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 358system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 359system.cpu.dcache.fast_writes 0 # number of fast writes performed 360system.cpu.dcache.cache_copies 0 # number of cache copies performed 361system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 362system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 363system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 364system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 365system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 366system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 367system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 368system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses 369system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles 370system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles 371system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles 372system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles 373system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles 374system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles 375system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles 376system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles 377system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 378system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 379system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 380system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 381system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 382system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 383system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 384system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses 385system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency 386system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency 387system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 388system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 389system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 390system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 391system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 392system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 393system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 394system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) 395system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution 396system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 397system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 399system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 400system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 401system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) 402system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) 403system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 404system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) 405system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) 406system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 407system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 408system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 409system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 410system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 411system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 412system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 413 414---------- End Simulation Statistics ----------	107system.cpu.icache.tags.replacements 0 # number of replacements 108system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use 109system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 110system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 111system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 112system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 113system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor 114system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy 115system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy 116system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 117system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 118system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 119system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 120system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 121system.cpu.icache.tags.data_accesses 10999 # Number of data accesses 122system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 123system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 124system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 125system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 126system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 127system.cpu.icache.overall_hits::total 5114 # number of overall hits 128system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 129system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 130system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 131system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 132system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 133system.cpu.icache.overall_misses::total 257 # number of overall misses 134system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles 135system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles 136system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles 137system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles 138system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles 139system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles 140system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 141system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 142system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 143system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 144system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 145system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 146system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 147system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 148system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 149system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 150system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 151system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses 152system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency 153system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency 154system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 155system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency 156system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 157system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency 158system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 161system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 162system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 163system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 164system.cpu.icache.fast_writes 0 # number of fast writes performed 165system.cpu.icache.cache_copies 0 # number of cache copies performed 166system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 167system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 168system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 169system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 170system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 171system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses 172system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles 173system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles 174system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles 175system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles 176system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles 177system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles 178system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 179system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 180system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 181system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 182system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 183system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 184system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency 185system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency 186system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 187system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 188system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 189system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 190system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 191system.cpu.l2cache.tags.replacements 0 # number of replacements 192system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use 193system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 194system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 195system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 196system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 197system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor 198system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor 199system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy 200system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy 201system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy 202system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 203system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 204system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 205system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 206system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 207system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses 208system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 209system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 210system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 211system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 212system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 213system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 214system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 215system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 216system.cpu.l2cache.overall_hits::total 3 # number of overall hits 217system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses 218system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 219system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses 220system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses 221system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses 222system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 223system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 224system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 225system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 226system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 227system.cpu.l2cache.overall_misses::total 389 # number of overall misses 228system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles 229system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles 230system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles 231system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles 232system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles 233system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles 234system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 235system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles 236system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles 237system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 238system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles 239system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) 240system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) 241system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) 242system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 243system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 244system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 245system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 246system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses 247system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses 248system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 249system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses 250system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses 251system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses 252system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses 253system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 254system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 255system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 256system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 257system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 258system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 259system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 260system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses 261system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 262system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 263system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 264system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 265system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 266system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 267system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 268system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 269system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 270system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 271system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 272system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 273system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 275system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 276system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 277system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 278system.cpu.l2cache.fast_writes 0 # number of fast writes performed 279system.cpu.l2cache.cache_copies 0 # number of cache copies performed 280system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses 281system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 282system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses 283system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 284system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 285system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 286system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 287system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 288system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 289system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 290system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses 291system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles 292system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles 293system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles 294system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles 295system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles 296system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles 297system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 298system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles 299system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles 300system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 301system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles 302system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses 303system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses 304system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses 305system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 306system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 307system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 308system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 309system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 310system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 311system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 312system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses 313system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 314system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 315system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 316system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 317system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 318system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 319system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 320system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 321system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 322system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 323system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 324system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.cpu.dcache.tags.replacements 0 # number of replacements 326system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use 327system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 328system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 329system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 330system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 331system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor 332system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy 333system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy 334system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 335system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 336system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 337system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 338system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 339system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses 340system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 341system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 342system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 343system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 344system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 345system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 346system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 347system.cpu.dcache.overall_hits::total 1253 # number of overall hits 348system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 349system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 350system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 351system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 352system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 353system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 354system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 355system.cpu.dcache.overall_misses::total 135 # number of overall misses 356system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles 357system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles 358system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles 359system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles 360system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles 361system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles 362system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles 363system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles 364system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 365system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 366system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 367system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 368system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 369system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 370system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 371system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 372system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 373system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 374system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 375system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 376system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 377system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 378system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 379system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses 380system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency 381system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency 382system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 383system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 384system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 385system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency 386system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 387system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency 388system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 389system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 390system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 391system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 392system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 393system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 394system.cpu.dcache.fast_writes 0 # number of fast writes performed 395system.cpu.dcache.cache_copies 0 # number of cache copies performed 396system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 397system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 398system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 399system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 400system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 401system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 402system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 403system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses 404system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles 405system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles 406system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles 407system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles 408system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles 409system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles 410system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles 411system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles 412system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 413system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 414system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 415system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 416system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 417system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 418system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 419system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses 420system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency 421system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency 422system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 423system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 424system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 425system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 426system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 427system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 428system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 429system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) 430system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 434system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 435system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) 438system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) 441system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 442system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 443system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 444system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 445system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 446system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 447system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 448 449---------- End Simulation Statistics ----------