1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 27800500 # Number of ticks simulated
5final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 510787 # Simulator instruction rate (inst/s)
8host_op_rate 510102 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2658808340 # Simulator tick rate (ticks/s)
10host_mem_usage 289420 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5327 # Number of instructions simulated
13sim_ops 5327 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 11 # Number of system calls
34system.cpu.numCycles 55601 # number of cpu cycles simulated
35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 5327 # Number of instructions committed
38system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
41system.cpu.num_func_calls 146 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
43system.cpu.num_int_insts 4505 # number of integer instructions
44system.cpu.num_fp_insts 0 # number of float instructions
45system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
46system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
49system.cpu.num_mem_refs 1401 # number of memory refs
50system.cpu.num_load_insts 723 # Number of load instructions
51system.cpu.num_store_insts 678 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
53system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 1121 # Number of branches fetched
57system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
58system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
61system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
84system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
87system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
88system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 5370 # Class of executed instruction
92system.cpu.dcache.tags.replacements 0 # number of replacements
93system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use
94system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
98system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor
99system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
104system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
105system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
106system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
107system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
108system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
109system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
110system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
111system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
112system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
113system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
114system.cpu.dcache.overall_hits::total 1253 # number of overall hits
115system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
116system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
117system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
118system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
119system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
120system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
121system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
122system.cpu.dcache.overall_misses::total 135 # number of overall misses
123system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
124system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
125system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
126system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
127system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
128system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
129system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
130system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
131system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
132system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
133system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
134system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
135system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
136system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
137system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
138system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
139system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
140system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
141system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
142system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
143system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
144system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
145system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
146system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
147system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
148system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
149system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
150system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
151system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
152system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
153system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
154system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
155system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
156system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
157system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
158system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
159system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
160system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
161system.cpu.dcache.fast_writes 0 # number of fast writes performed
162system.cpu.dcache.cache_copies 0 # number of cache copies performed
163system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
164system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
165system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
166system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
167system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
168system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
169system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
170system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
171system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles
172system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles
173system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles
174system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles
175system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles
176system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles
177system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles
178system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles
179system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
183system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
184system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
185system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
186system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
187system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency
188system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency
189system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
192system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
193system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
194system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
195system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
196system.cpu.icache.tags.replacements 0 # number of replacements
197system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use
198system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
199system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
200system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
201system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor
203system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy
204system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy
205system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
206system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
207system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
208system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
209system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
210system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
211system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
212system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
213system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
214system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
215system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
216system.cpu.icache.overall_hits::total 5114 # number of overall hits
217system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
218system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
219system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
220system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
221system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
222system.cpu.icache.overall_misses::total 257 # number of overall misses
223system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
224system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
225system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
226system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
227system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
228system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
229system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
230system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
231system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
232system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
233system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
234system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
236system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
237system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
238system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
239system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
240system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
241system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
242system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
243system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
244system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
245system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
246system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
253system.cpu.icache.fast_writes 0 # number of fast writes performed
254system.cpu.icache.cache_copies 0 # number of cache copies performed
255system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
256system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
257system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
258system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
259system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
260system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
261system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles
262system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles
263system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles
264system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles
265system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles
266system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles
267system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
268system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
269system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
270system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
271system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
272system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
273system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency
274system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency
275system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
276system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
277system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
278system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
279system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
280system.cpu.l2cache.tags.replacements 0 # number of replacements
281system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use
282system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
283system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
284system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
285system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
286system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor
287system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor
288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
289system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
290system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
291system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
292system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
293system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
294system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
295system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
--- 13 unchanged lines hidden (view full) ---
309system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
310system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
311system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
312system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
313system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
314system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
315system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
316system.cpu.l2cache.overall_misses::total 389 # number of overall misses
317system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles
318system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
319system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles
320system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
321system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
322system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
323system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
324system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
325system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
326system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
327system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
328system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses)
329system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
330system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses)
331system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
332system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
333system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
334system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
335system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
--- 6 unchanged lines hidden (view full) ---
342system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
343system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
344system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
345system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
346system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
347system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
348system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
349system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
350system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency
351system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
352system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency
353system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
354system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
355system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
356system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
357system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
358system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
359system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
360system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
361system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
364system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
365system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367system.cpu.l2cache.fast_writes 0 # number of fast writes performed
368system.cpu.l2cache.cache_copies 0 # number of cache copies performed
369system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses
370system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
371system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses
372system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
373system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
374system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
375system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
376system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
377system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
378system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
379system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
380system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles
381system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
382system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles
383system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles
384system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles
385system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles
386system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
387system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles
388system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles
389system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
390system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles
391system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
392system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
393system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses
394system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
395system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
396system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
397system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
398system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
399system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
400system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
401system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
402system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
403system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
404system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
405system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
406system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
407system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
408system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
409system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
410system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
411system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
412system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
413system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
414system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution
415system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
416system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
417system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
418system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
419system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
420system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
421system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
--- 12 unchanged lines hidden (view full) ---
434system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
435system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
436system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
437system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
438system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
439system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
440system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
441system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
442system.membus.trans_dist::ReadReq 308 # Transaction distribution
443system.membus.trans_dist::ReadResp 308 # Transaction distribution
444system.membus.trans_dist::ReadExReq 81 # Transaction distribution
445system.membus.trans_dist::ReadExResp 81 # Transaction distribution
446system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
447system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
448system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
449system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
450system.membus.snoops 0 # Total snoops (count)
451system.membus.snoop_fanout::samples 389 # Request fanout histogram
452system.membus.snoop_fanout::mean 0 # Request fanout histogram
453system.membus.snoop_fanout::stdev 0 # Request fanout histogram
454system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
455system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
456system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
457system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
458system.membus.snoop_fanout::min_value 0 # Request fanout histogram
459system.membus.snoop_fanout::max_value 0 # Request fanout histogram
460system.membus.snoop_fanout::total 389 # Request fanout histogram
461system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
462system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
463system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
464system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
465
466---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 27800500 # Number of ticks simulated
5final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 510787 # Simulator instruction rate (inst/s)
8host_op_rate 510102 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2658808340 # Simulator tick rate (ticks/s)
10host_mem_usage 289420 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5327 # Number of instructions simulated
13sim_ops 5327 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 11 # Number of system calls
34system.cpu.numCycles 55601 # number of cpu cycles simulated
35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 5327 # Number of instructions committed
38system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
41system.cpu.num_func_calls 146 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
43system.cpu.num_int_insts 4505 # number of integer instructions
44system.cpu.num_fp_insts 0 # number of float instructions
45system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
46system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
49system.cpu.num_mem_refs 1401 # number of memory refs
50system.cpu.num_load_insts 723 # Number of load instructions
51system.cpu.num_store_insts 678 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
53system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 1121 # Number of branches fetched
57system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
58system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
61system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
84system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
87system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
88system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 5370 # Class of executed instruction
92system.cpu.dcache.tags.replacements 0 # number of replacements
93system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use
94system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
98system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor
99system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
104system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
105system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
106system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
107system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
108system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
109system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
110system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
111system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
112system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
113system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
114system.cpu.dcache.overall_hits::total 1253 # number of overall hits
115system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
116system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
117system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
118system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
119system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
120system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
121system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
122system.cpu.dcache.overall_misses::total 135 # number of overall misses
123system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
124system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
125system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
126system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
127system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
128system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
129system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
130system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
131system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
132system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
133system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
134system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
135system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
136system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
137system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
138system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
139system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
140system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
141system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
142system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
143system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
144system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
145system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
146system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
147system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
148system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
149system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
150system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
151system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
152system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
153system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
154system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
155system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
156system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
157system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
158system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
159system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
160system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
161system.cpu.dcache.fast_writes 0 # number of fast writes performed
162system.cpu.dcache.cache_copies 0 # number of cache copies performed
163system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
164system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
165system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
166system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
167system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
168system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
169system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
170system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
171system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles
172system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles
173system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles
174system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles
175system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles
176system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles
177system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles
178system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles
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180system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
183system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
184system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
185system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
186system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
187system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency
188system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency
189system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
192system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
193system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency
194system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency
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196system.cpu.icache.tags.replacements 0 # number of replacements
197system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use
198system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
199system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
200system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
201system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor
203system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy
204system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy
205system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
206system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
207system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
208system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
209system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
210system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
211system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
212system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
213system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
214system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
215system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
216system.cpu.icache.overall_hits::total 5114 # number of overall hits
217system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
218system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
219system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
220system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
221system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
222system.cpu.icache.overall_misses::total 257 # number of overall misses
223system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
224system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
225system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
226system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
227system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
228system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
229system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
230system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
231system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
232system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
233system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
234system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
236system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
237system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
238system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
239system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
240system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
241system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
242system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
243system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
244system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
245system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
246system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
253system.cpu.icache.fast_writes 0 # number of fast writes performed
254system.cpu.icache.cache_copies 0 # number of cache copies performed
255system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
256system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
257system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
258system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
259system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
260system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
261system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles
262system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles
263system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles
264system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles
265system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles
266system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles
267system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
268system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
269system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
270system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
271system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
272system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
273system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency
274system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency
275system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
276system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
277system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency
278system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency
279system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
280system.cpu.l2cache.tags.replacements 0 # number of replacements
281system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use
282system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
283system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
284system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
285system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
286system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor
287system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor
288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
289system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
290system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
291system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
292system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
293system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
294system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
295system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
--- 13 unchanged lines hidden (view full) ---
309system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
310system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
311system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
312system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
313system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
314system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
315system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
316system.cpu.l2cache.overall_misses::total 389 # number of overall misses
317system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles
318system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
319system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles
320system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
321system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
322system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
323system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
324system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
325system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
326system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
327system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
328system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses)
329system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
330system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses)
331system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
332system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
333system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
334system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
335system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
--- 6 unchanged lines hidden (view full) ---
342system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
343system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
344system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
345system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
346system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
347system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
348system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
349system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
350system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency
351system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
352system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency
353system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
354system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
355system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
356system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
357system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
358system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
359system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
360system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
361system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
364system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
365system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367system.cpu.l2cache.fast_writes 0 # number of fast writes performed
368system.cpu.l2cache.cache_copies 0 # number of cache copies performed
369system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses
370system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
371system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses
372system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
373system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
374system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
375system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
376system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
377system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
378system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
379system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
380system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles
381system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
382system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles
383system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles
384system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles
385system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles
386system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
387system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles
388system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles
389system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
390system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles
391system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
392system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
393system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses
394system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
395system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
396system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
397system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
398system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
399system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
400system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
401system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
402system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
403system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
404system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
405system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
406system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
407system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
408system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
409system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
410system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
411system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
412system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
413system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
414system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution
415system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
416system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
417system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
418system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
419system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
420system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
421system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
--- 12 unchanged lines hidden (view full) ---
434system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
435system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
436system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
437system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
438system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
439system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
440system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
441system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
442system.membus.trans_dist::ReadReq 308 # Transaction distribution
443system.membus.trans_dist::ReadResp 308 # Transaction distribution
444system.membus.trans_dist::ReadExReq 81 # Transaction distribution
445system.membus.trans_dist::ReadExResp 81 # Transaction distribution
446system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
447system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
448system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
449system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
450system.membus.snoops 0 # Total snoops (count)
451system.membus.snoop_fanout::samples 389 # Request fanout histogram
452system.membus.snoop_fanout::mean 0 # Request fanout histogram
453system.membus.snoop_fanout::stdev 0 # Request fanout histogram
454system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
455system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram
456system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
457system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
458system.membus.snoop_fanout::min_value 0 # Request fanout histogram
459system.membus.snoop_fanout::max_value 0 # Request fanout histogram
460system.membus.snoop_fanout::total 389 # Request fanout histogram
461system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
462system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
463system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
464system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
465
466---------- End Simulation Statistics ----------