| config.ini (9276:a5ede748a1d9) | config.ini (9348:44d31345e360) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 | 13clock=1000 |
| 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 34 unchanged lines hidden (view full) --- 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 34 unchanged lines hidden (view full) --- 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 |
| 64clock=1 | 64clock=500 |
| 65forward_snoops=true 66hash_delay=1 | 65forward_snoops=true 66hash_delay=1 |
| 67hit_latency=1000 | 67hit_latency=2 |
| 68is_top_level=true 69max_miss_count=0 | 68is_top_level=true 69max_miss_count=0 |
| 70mshrs=10 | 70mshrs=4 |
| 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null | 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null |
| 75response_latency=1000 | 75response_latency=2 |
| 76size=262144 77subblock_size=0 78system=system | 76size=262144 77subblock_size=0 78system=system |
| 79tgts_per_mshr=5 | 79tgts_per_mshr=20 |
| 80trace_addr=0 81two_queue=false 82write_buffers=8 83cpu_side=system.cpu.dcache_port 84mem_side=system.cpu.toL2Bus.slave[1] 85 86[system.cpu.dtb] 87type=SparcTLB 88size=64 89 90[system.cpu.icache] 91type=BaseCache 92addr_ranges=0:18446744073709551615 93assoc=2 94block_size=64 | 80trace_addr=0 81two_queue=false 82write_buffers=8 83cpu_side=system.cpu.dcache_port 84mem_side=system.cpu.toL2Bus.slave[1] 85 86[system.cpu.dtb] 87type=SparcTLB 88size=64 89 90[system.cpu.icache] 91type=BaseCache 92addr_ranges=0:18446744073709551615 93assoc=2 94block_size=64 |
| 95clock=1 | 95clock=500 |
| 96forward_snoops=true 97hash_delay=1 | 96forward_snoops=true 97hash_delay=1 |
| 98hit_latency=1000 | 98hit_latency=2 |
| 99is_top_level=true 100max_miss_count=0 | 99is_top_level=true 100max_miss_count=0 |
| 101mshrs=10 | 101mshrs=4 |
| 102prefetch_on_access=false 103prefetcher=Null 104prioritizeRequests=false 105repl=Null | 102prefetch_on_access=false 103prefetcher=Null 104prioritizeRequests=false 105repl=Null |
| 106response_latency=1000 | 106response_latency=2 |
| 107size=131072 108subblock_size=0 109system=system | 107size=131072 108subblock_size=0 109system=system |
| 110tgts_per_mshr=5 | 110tgts_per_mshr=20 |
| 111trace_addr=0 112two_queue=false 113write_buffers=8 114cpu_side=system.cpu.icache_port 115mem_side=system.cpu.toL2Bus.slave[0] 116 117[system.cpu.interrupts] 118type=SparcInterrupts 119 120[system.cpu.itb] 121type=SparcTLB 122size=64 123 124[system.cpu.l2cache] 125type=BaseCache 126addr_ranges=0:18446744073709551615 | 111trace_addr=0 112two_queue=false 113write_buffers=8 114cpu_side=system.cpu.icache_port 115mem_side=system.cpu.toL2Bus.slave[0] 116 117[system.cpu.interrupts] 118type=SparcInterrupts 119 120[system.cpu.itb] 121type=SparcTLB 122size=64 123 124[system.cpu.l2cache] 125type=BaseCache 126addr_ranges=0:18446744073709551615 |
| 127assoc=2 | 127assoc=8 |
| 128block_size=64 | 128block_size=64 |
| 129clock=1 | 129clock=500 |
| 130forward_snoops=true 131hash_delay=1 | 130forward_snoops=true 131hash_delay=1 |
| 132hit_latency=10000 | 132hit_latency=20 |
| 133is_top_level=false 134max_miss_count=0 | 133is_top_level=false 134max_miss_count=0 |
| 135mshrs=10 | 135mshrs=20 |
| 136prefetch_on_access=false 137prefetcher=Null 138prioritizeRequests=false 139repl=Null | 136prefetch_on_access=false 137prefetcher=Null 138prioritizeRequests=false 139repl=Null |
| 140response_latency=10000 | 140response_latency=20 |
| 141size=2097152 142subblock_size=0 143system=system | 141size=2097152 142subblock_size=0 143system=system |
| 144tgts_per_mshr=5 | 144tgts_per_mshr=12 |
| 145trace_addr=0 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.toL2Bus.master[0] 149mem_side=system.membus.slave[1] 150 151[system.cpu.toL2Bus] 152type=CoherentBus 153block_size=64 | 145trace_addr=0 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.toL2Bus.master[0] 149mem_side=system.membus.slave[1] 150 151[system.cpu.toL2Bus] 152type=CoherentBus 153block_size=64 |
| 154clock=1000 | 154clock=500 |
| 155header_cycles=1 156use_default_range=false | 155header_cycles=1 156use_default_range=false |
| 157width=8 | 157width=32 |
| 158master=system.cpu.l2cache.cpu_side 159slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 160 161[system.cpu.tracer] 162type=ExeTracer 163 164[system.cpu.workload] 165type=LiveProcess 166cmd=hello 167cwd= 168egid=100 169env= 170errout=cerr 171euid=100 | 158master=system.cpu.l2cache.cpu_side 159slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 160 161[system.cpu.tracer] 162type=ExeTracer 163 164[system.cpu.workload] 165type=LiveProcess 166cmd=hello 167cwd= 168egid=100 169env= 170errout=cerr 171euid=100 |
| 172executable=tests/test-progs/hello/bin/sparc/linux/hello | 172executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello |
| 173gid=100 174input=cin 175max_stack_size=67108864 176output=cout 177pid=100 178ppid=99 179simpoint=0 180system=system --- 7 unchanged lines hidden (view full) --- 188use_default_range=false 189width=8 190master=system.physmem.port 191slave=system.system_port system.cpu.l2cache.mem_side 192 193[system.physmem] 194type=SimpleMemory 195bandwidth=73.000000 | 173gid=100 174input=cin 175max_stack_size=67108864 176output=cout 177pid=100 178ppid=99 179simpoint=0 180system=system --- 7 unchanged lines hidden (view full) --- 188use_default_range=false 189width=8 190master=system.physmem.port 191slave=system.system_port system.cpu.l2cache.mem_side 192 193[system.physmem] 194type=SimpleMemory 195bandwidth=73.000000 |
| 196clock=1 | 196clock=1000 |
| 197conf_table_reported=false 198in_addr_map=true 199latency=30000 200latency_var=0 201null=false 202range=0:134217727 203zero=false 204port=system.membus.master[0] 205 | 197conf_table_reported=false 198in_addr_map=true 199latency=30000 200latency_var=0 201null=false 202range=0:134217727 203zero=false 204port=system.membus.master[0] 205 |