| stats.txt (12062:d6ee16239a26) | stats.txt (12137:d877205ec1bc) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000034 4sim_ticks 34045500 5final_tick 34045500 | 3sim_seconds 0.000032 4sim_ticks 31821500 5final_tick 31821500 |
| 6sim_freq 1000000000000 | 6sim_freq 1000000000000 |
| 7host_inst_rate 83295 8host_op_rate 83403 9host_tick_rate 510821707 10host_mem_usage 275396 11host_seconds 0.07 12sim_insts 5550 13sim_ops 5558 | 7host_inst_rate 11620 8host_op_rate 11638 9host_tick_rate 66593131 10host_mem_usage 258956 11host_seconds 0.48 12sim_insts 5552 13sim_ops 5561 |
| 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 | 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 34045500 17system.physmem.bytes_read::cpu.inst 17856 18system.physmem.bytes_read::cpu.data 9280 19system.physmem.bytes_read::total 27136 20system.physmem.bytes_inst_read::cpu.inst 17856 21system.physmem.bytes_inst_read::total 17856 22system.physmem.num_reads::cpu.inst 279 23system.physmem.num_reads::cpu.data 145 24system.physmem.num_reads::total 424 25system.physmem.bw_read::cpu.inst 524474600 26system.physmem.bw_read::cpu.data 272576405 27system.physmem.bw_read::total 797051005 28system.physmem.bw_inst_read::cpu.inst 524474600 29system.physmem.bw_inst_read::total 524474600 30system.physmem.bw_total::cpu.inst 524474600 31system.physmem.bw_total::cpu.data 272576405 32system.physmem.bw_total::total 797051005 33system.pwrStateResidencyTicks::UNDEFINED 34045500 | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 31821500 17system.physmem.bytes_read::cpu.inst 14592 18system.physmem.bytes_read::cpu.data 9216 19system.physmem.bytes_read::total 23808 20system.physmem.bytes_inst_read::cpu.inst 14592 21system.physmem.bytes_inst_read::total 14592 22system.physmem.num_reads::cpu.inst 228 23system.physmem.num_reads::cpu.data 144 24system.physmem.num_reads::total 372 25system.physmem.bw_read::cpu.inst 458557893 26system.physmem.bw_read::cpu.data 289615512 27system.physmem.bw_read::total 748173405 28system.physmem.bw_inst_read::cpu.inst 458557893 29system.physmem.bw_inst_read::total 458557893 30system.physmem.bw_total::cpu.inst 458557893 31system.physmem.bw_total::cpu.data 289615512 32system.physmem.bw_total::total 748173405 33system.pwrStateResidencyTicks::UNDEFINED 31821500 |
| 34system.cpu_clk_domain.clock 500 35system.cpu.dtb.read_hits 0 36system.cpu.dtb.read_misses 0 37system.cpu.dtb.read_accesses 0 38system.cpu.dtb.write_hits 0 39system.cpu.dtb.write_misses 0 40system.cpu.dtb.write_accesses 0 41system.cpu.dtb.hits 0 --- 4 unchanged lines hidden (view full) --- 46system.cpu.itb.read_accesses 0 47system.cpu.itb.write_hits 0 48system.cpu.itb.write_misses 0 49system.cpu.itb.write_accesses 0 50system.cpu.itb.hits 0 51system.cpu.itb.misses 0 52system.cpu.itb.accesses 0 53system.cpu.workload.numSyscalls 9 | 34system.cpu_clk_domain.clock 500 35system.cpu.dtb.read_hits 0 36system.cpu.dtb.read_misses 0 37system.cpu.dtb.read_accesses 0 38system.cpu.dtb.write_hits 0 39system.cpu.dtb.write_misses 0 40system.cpu.dtb.write_accesses 0 41system.cpu.dtb.hits 0 --- 4 unchanged lines hidden (view full) --- 46system.cpu.itb.read_accesses 0 47system.cpu.itb.write_hits 0 48system.cpu.itb.write_misses 0 49system.cpu.itb.write_accesses 0 50system.cpu.itb.hits 0 51system.cpu.itb.misses 0 52system.cpu.itb.accesses 0 53system.cpu.workload.numSyscalls 9 |
| 54system.cpu.pwrStateResidencyTicks::ON 34045500 55system.cpu.numCycles 68091 | 54system.cpu.pwrStateResidencyTicks::ON 31821500 55system.cpu.numCycles 63643 |
| 56system.cpu.numWorkItemsStarted 0 57system.cpu.numWorkItemsCompleted 0 | 56system.cpu.numWorkItemsStarted 0 57system.cpu.numWorkItemsCompleted 0 |
| 58system.cpu.committedInsts 5550 59system.cpu.committedOps 5558 60system.cpu.num_int_alu_accesses 5557 | 58system.cpu.committedInsts 5552 59system.cpu.committedOps 5561 60system.cpu.num_int_alu_accesses 5498 |
| 61system.cpu.num_fp_alu_accesses 12 | 61system.cpu.num_fp_alu_accesses 12 |
| 62system.cpu.num_func_calls 291 | 62system.cpu.num_vec_alu_accesses 0 63system.cpu.num_func_calls 282 |
| 63system.cpu.num_conditional_control_insts 914 | 64system.cpu.num_conditional_control_insts 914 |
| 64system.cpu.num_int_insts 5557 | 65system.cpu.num_int_insts 5498 |
| 65system.cpu.num_fp_insts 12 | 66system.cpu.num_fp_insts 12 |
| 66system.cpu.num_int_register_reads 7540 67system.cpu.num_int_register_writes 3562 | 67system.cpu.num_vec_insts 0 68system.cpu.num_int_register_reads 7038 69system.cpu.num_int_register_writes 3414 |
| 68system.cpu.num_fp_register_reads 12 69system.cpu.num_fp_register_writes 0 | 70system.cpu.num_fp_register_reads 12 71system.cpu.num_fp_register_writes 0 |
| 70system.cpu.num_mem_refs 2198 71system.cpu.num_load_insts 1101 72system.cpu.num_store_insts 1097 | 72system.cpu.num_vec_register_reads 0 73system.cpu.num_vec_register_writes 0 74system.cpu.num_mem_refs 2162 75system.cpu.num_load_insts 1082 76system.cpu.num_store_insts 1080 |
| 73system.cpu.num_idle_cycles 0 | 77system.cpu.num_idle_cycles 0 |
| 74system.cpu.num_busy_cycles 68091 | 78system.cpu.num_busy_cycles 63643 |
| 75system.cpu.not_idle_fraction 1 76system.cpu.idle_fraction 0 | 79system.cpu.not_idle_fraction 1 80system.cpu.idle_fraction 0 |
| 77system.cpu.Branches 1205 | 81system.cpu.Branches 1196 |
| 78system.cpu.op_class::No_OpClass 10 0.18% 0.18% | 82system.cpu.op_class::No_OpClass 10 0.18% 0.18% |
| 79system.cpu.op_class::IntAlu 3353 60.23% 60.41% 80system.cpu.op_class::IntMult 2 0.04% 60.45% 81system.cpu.op_class::IntDiv 4 0.07% 60.52% 82system.cpu.op_class::FloatAdd 0 0.00% 60.52% 83system.cpu.op_class::FloatCmp 0 0.00% 60.52% 84system.cpu.op_class::FloatCvt 0 0.00% 60.52% 85system.cpu.op_class::FloatMult 0 0.00% 60.52% 86system.cpu.op_class::FloatMultAcc 0 0.00% 60.52% 87system.cpu.op_class::FloatDiv 0 0.00% 60.52% 88system.cpu.op_class::FloatMisc 0 0.00% 60.52% 89system.cpu.op_class::FloatSqrt 0 0.00% 60.52% 90system.cpu.op_class::SimdAdd 0 0.00% 60.52% 91system.cpu.op_class::SimdAddAcc 0 0.00% 60.52% 92system.cpu.op_class::SimdAlu 0 0.00% 60.52% 93system.cpu.op_class::SimdCmp 0 0.00% 60.52% 94system.cpu.op_class::SimdCvt 0 0.00% 60.52% 95system.cpu.op_class::SimdMisc 0 0.00% 60.52% 96system.cpu.op_class::SimdMult 0 0.00% 60.52% 97system.cpu.op_class::SimdMultAcc 0 0.00% 60.52% 98system.cpu.op_class::SimdShift 0 0.00% 60.52% 99system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52% 100system.cpu.op_class::SimdSqrt 0 0.00% 60.52% 101system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52% 102system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52% 103system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52% 104system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52% 105system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52% 106system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52% 107system.cpu.op_class::SimdFloatMult 0 0.00% 60.52% 108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52% 109system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52% 110system.cpu.op_class::MemRead 1101 19.78% 80.29% 111system.cpu.op_class::MemWrite 1085 19.49% 99.78% | 83system.cpu.op_class::IntAlu 3392 60.90% 61.08% 84system.cpu.op_class::IntMult 2 0.04% 61.11% 85system.cpu.op_class::IntDiv 4 0.07% 61.18% 86system.cpu.op_class::FloatAdd 0 0.00% 61.18% 87system.cpu.op_class::FloatCmp 0 0.00% 61.18% 88system.cpu.op_class::FloatCvt 0 0.00% 61.18% 89system.cpu.op_class::FloatMult 0 0.00% 61.18% 90system.cpu.op_class::FloatMultAcc 0 0.00% 61.18% 91system.cpu.op_class::FloatDiv 0 0.00% 61.18% 92system.cpu.op_class::FloatMisc 0 0.00% 61.18% 93system.cpu.op_class::FloatSqrt 0 0.00% 61.18% 94system.cpu.op_class::SimdAdd 0 0.00% 61.18% 95system.cpu.op_class::SimdAddAcc 0 0.00% 61.18% 96system.cpu.op_class::SimdAlu 0 0.00% 61.18% 97system.cpu.op_class::SimdCmp 0 0.00% 61.18% 98system.cpu.op_class::SimdCvt 0 0.00% 61.18% 99system.cpu.op_class::SimdMisc 0 0.00% 61.18% 100system.cpu.op_class::SimdMult 0 0.00% 61.18% 101system.cpu.op_class::SimdMultAcc 0 0.00% 61.18% 102system.cpu.op_class::SimdShift 0 0.00% 61.18% 103system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18% 104system.cpu.op_class::SimdSqrt 0 0.00% 61.18% 105system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18% 106system.cpu.op_class::SimdFloatAlu 0 0.00% 61.18% 107system.cpu.op_class::SimdFloatCmp 0 0.00% 61.18% 108system.cpu.op_class::SimdFloatCvt 0 0.00% 61.18% 109system.cpu.op_class::SimdFloatDiv 0 0.00% 61.18% 110system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18% 111system.cpu.op_class::SimdFloatMult 0 0.00% 61.18% 112system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18% 113system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18% 114system.cpu.op_class::MemRead 1082 19.43% 80.61% 115system.cpu.op_class::MemWrite 1068 19.17% 99.78% |
| 112system.cpu.op_class::FloatMemRead 0 0.00% 99.78% 113system.cpu.op_class::FloatMemWrite 12 0.22% 100.00% 114system.cpu.op_class::IprAccess 0 0.00% 100.00% 115system.cpu.op_class::InstPrefetch 0 0.00% 100.00% | 116system.cpu.op_class::FloatMemRead 0 0.00% 99.78% 117system.cpu.op_class::FloatMemWrite 12 0.22% 100.00% 118system.cpu.op_class::IprAccess 0 0.00% 100.00% 119system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| 116system.cpu.op_class::total 5567 117system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34045500 | 120system.cpu.op_class::total 5570 121system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31821500 |
| 118system.cpu.dcache.tags.replacements 0 | 122system.cpu.dcache.tags.replacements 0 |
| 119system.cpu.dcache.tags.tagsinuse 88.524153 120system.cpu.dcache.tags.total_refs 2053 121system.cpu.dcache.tags.sampled_refs 145 122system.cpu.dcache.tags.avg_refs 14.158621 | 123system.cpu.dcache.tags.tagsinuse 86.061155 124system.cpu.dcache.tags.total_refs 2018 125system.cpu.dcache.tags.sampled_refs 144 126system.cpu.dcache.tags.avg_refs 14.013889 |
| 123system.cpu.dcache.tags.warmup_cycle 0 | 127system.cpu.dcache.tags.warmup_cycle 0 |
| 124system.cpu.dcache.tags.occ_blocks::cpu.data 88.524153 125system.cpu.dcache.tags.occ_percent::cpu.data 0.021612 126system.cpu.dcache.tags.occ_percent::total 0.021612 127system.cpu.dcache.tags.occ_task_id_blocks::1024 145 128system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 129system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 130system.cpu.dcache.tags.occ_task_id_percent::1024 0.035400 131system.cpu.dcache.tags.tag_accesses 4541 132system.cpu.dcache.tags.data_accesses 4541 133system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34045500 134system.cpu.dcache.ReadReq_hits::cpu.data 1032 135system.cpu.dcache.ReadReq_hits::total 1032 136system.cpu.dcache.WriteReq_hits::cpu.data 1007 137system.cpu.dcache.WriteReq_hits::total 1007 138system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 139system.cpu.dcache.LoadLockedReq_hits::total 6 | 128system.cpu.dcache.tags.occ_blocks::cpu.data 86.061155 129system.cpu.dcache.tags.occ_percent::cpu.data 0.021011 130system.cpu.dcache.tags.occ_percent::total 0.021011 131system.cpu.dcache.tags.occ_task_id_blocks::1024 144 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 114 134system.cpu.dcache.tags.occ_task_id_percent::1024 0.035156 135system.cpu.dcache.tags.tag_accesses 4468 136system.cpu.dcache.tags.data_accesses 4468 137system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31821500 138system.cpu.dcache.ReadReq_hits::cpu.data 1013 139system.cpu.dcache.ReadReq_hits::total 1013 140system.cpu.dcache.WriteReq_hits::cpu.data 990 141system.cpu.dcache.WriteReq_hits::total 990 142system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 143system.cpu.dcache.LoadLockedReq_hits::total 7 |
| 140system.cpu.dcache.StoreCondReq_hits::cpu.data 8 141system.cpu.dcache.StoreCondReq_hits::total 8 | 144system.cpu.dcache.StoreCondReq_hits::cpu.data 8 145system.cpu.dcache.StoreCondReq_hits::total 8 |
| 142system.cpu.dcache.demand_hits::cpu.data 2039 143system.cpu.dcache.demand_hits::total 2039 144system.cpu.dcache.overall_hits::cpu.data 2039 145system.cpu.dcache.overall_hits::total 2039 | 146system.cpu.dcache.demand_hits::cpu.data 2003 147system.cpu.dcache.demand_hits::total 2003 148system.cpu.dcache.overall_hits::cpu.data 2003 149system.cpu.dcache.overall_hits::total 2003 |
| 146system.cpu.dcache.ReadReq_misses::cpu.data 61 147system.cpu.dcache.ReadReq_misses::total 61 148system.cpu.dcache.WriteReq_misses::cpu.data 82 149system.cpu.dcache.WriteReq_misses::total 82 | 150system.cpu.dcache.ReadReq_misses::cpu.data 61 151system.cpu.dcache.ReadReq_misses::total 61 152system.cpu.dcache.WriteReq_misses::cpu.data 82 153system.cpu.dcache.WriteReq_misses::total 82 |
| 150system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 151system.cpu.dcache.LoadLockedReq_misses::total 2 | 154system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 155system.cpu.dcache.LoadLockedReq_misses::total 1 |
| 152system.cpu.dcache.demand_misses::cpu.data 143 153system.cpu.dcache.demand_misses::total 143 154system.cpu.dcache.overall_misses::cpu.data 143 155system.cpu.dcache.overall_misses::total 143 156system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 157system.cpu.dcache.ReadReq_miss_latency::total 3843000 158system.cpu.dcache.WriteReq_miss_latency::cpu.data 5166000 159system.cpu.dcache.WriteReq_miss_latency::total 5166000 | 156system.cpu.dcache.demand_misses::cpu.data 143 157system.cpu.dcache.demand_misses::total 143 158system.cpu.dcache.overall_misses::cpu.data 143 159system.cpu.dcache.overall_misses::total 143 160system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 161system.cpu.dcache.ReadReq_miss_latency::total 3843000 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 5166000 163system.cpu.dcache.WriteReq_miss_latency::total 5166000 |
| 160system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 161system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 | 164system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000 165system.cpu.dcache.LoadLockedReq_miss_latency::total 63000 |
| 162system.cpu.dcache.demand_miss_latency::cpu.data 9009000 163system.cpu.dcache.demand_miss_latency::total 9009000 164system.cpu.dcache.overall_miss_latency::cpu.data 9009000 165system.cpu.dcache.overall_miss_latency::total 9009000 | 166system.cpu.dcache.demand_miss_latency::cpu.data 9009000 167system.cpu.dcache.demand_miss_latency::total 9009000 168system.cpu.dcache.overall_miss_latency::cpu.data 9009000 169system.cpu.dcache.overall_miss_latency::total 9009000 |
| 166system.cpu.dcache.ReadReq_accesses::cpu.data 1093 167system.cpu.dcache.ReadReq_accesses::total 1093 168system.cpu.dcache.WriteReq_accesses::cpu.data 1089 169system.cpu.dcache.WriteReq_accesses::total 1089 | 170system.cpu.dcache.ReadReq_accesses::cpu.data 1074 171system.cpu.dcache.ReadReq_accesses::total 1074 172system.cpu.dcache.WriteReq_accesses::cpu.data 1072 173system.cpu.dcache.WriteReq_accesses::total 1072 |
| 170system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 171system.cpu.dcache.LoadLockedReq_accesses::total 8 172system.cpu.dcache.StoreCondReq_accesses::cpu.data 8 173system.cpu.dcache.StoreCondReq_accesses::total 8 | 174system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 175system.cpu.dcache.LoadLockedReq_accesses::total 8 176system.cpu.dcache.StoreCondReq_accesses::cpu.data 8 177system.cpu.dcache.StoreCondReq_accesses::total 8 |
| 174system.cpu.dcache.demand_accesses::cpu.data 2182 175system.cpu.dcache.demand_accesses::total 2182 176system.cpu.dcache.overall_accesses::cpu.data 2182 177system.cpu.dcache.overall_accesses::total 2182 178system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.055810 179system.cpu.dcache.ReadReq_miss_rate::total 0.055810 180system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.075298 181system.cpu.dcache.WriteReq_miss_rate::total 0.075298 182system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 183system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 184system.cpu.dcache.demand_miss_rate::cpu.data 0.065536 185system.cpu.dcache.demand_miss_rate::total 0.065536 186system.cpu.dcache.overall_miss_rate::cpu.data 0.065536 187system.cpu.dcache.overall_miss_rate::total 0.065536 | 178system.cpu.dcache.demand_accesses::cpu.data 2146 179system.cpu.dcache.demand_accesses::total 2146 180system.cpu.dcache.overall_accesses::cpu.data 2146 181system.cpu.dcache.overall_accesses::total 2146 182system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.056797 183system.cpu.dcache.ReadReq_miss_rate::total 0.056797 184system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.076493 185system.cpu.dcache.WriteReq_miss_rate::total 0.076493 186system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 187system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 188system.cpu.dcache.demand_miss_rate::cpu.data 0.066636 189system.cpu.dcache.demand_miss_rate::total 0.066636 190system.cpu.dcache.overall_miss_rate::cpu.data 0.066636 191system.cpu.dcache.overall_miss_rate::total 0.066636 |
| 188system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 189system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 190system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 191system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 192system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 193system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 194system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 195system.cpu.dcache.demand_avg_miss_latency::total 63000 --- 4 unchanged lines hidden (view full) --- 200system.cpu.dcache.blocked::no_mshrs 0 201system.cpu.dcache.blocked::no_targets 0 202system.cpu.dcache.avg_blocked_cycles::no_mshrs nan 203system.cpu.dcache.avg_blocked_cycles::no_targets nan 204system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 205system.cpu.dcache.ReadReq_mshr_misses::total 61 206system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 207system.cpu.dcache.WriteReq_mshr_misses::total 82 | 192system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 193system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 194system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 195system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 196system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 197system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 198system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 199system.cpu.dcache.demand_avg_miss_latency::total 63000 --- 4 unchanged lines hidden (view full) --- 204system.cpu.dcache.blocked::no_mshrs 0 205system.cpu.dcache.blocked::no_targets 0 206system.cpu.dcache.avg_blocked_cycles::no_mshrs nan 207system.cpu.dcache.avg_blocked_cycles::no_targets nan 208system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 209system.cpu.dcache.ReadReq_mshr_misses::total 61 210system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 211system.cpu.dcache.WriteReq_mshr_misses::total 82 |
| 208system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 209system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 | 212system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 213system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 |
| 210system.cpu.dcache.demand_mshr_misses::cpu.data 143 211system.cpu.dcache.demand_mshr_misses::total 143 212system.cpu.dcache.overall_mshr_misses::cpu.data 143 213system.cpu.dcache.overall_mshr_misses::total 143 214system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 215system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 216system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084000 217system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084000 | 214system.cpu.dcache.demand_mshr_misses::cpu.data 143 215system.cpu.dcache.demand_mshr_misses::total 143 216system.cpu.dcache.overall_mshr_misses::cpu.data 143 217system.cpu.dcache.overall_mshr_misses::total 143 218system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 219system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 220system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084000 221system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084000 |
| 218system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 124000 219system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 124000 | 222system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000 223system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000 |
| 220system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8866000 221system.cpu.dcache.demand_mshr_miss_latency::total 8866000 222system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8866000 223system.cpu.dcache.overall_mshr_miss_latency::total 8866000 | 224system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8866000 225system.cpu.dcache.demand_mshr_miss_latency::total 8866000 226system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8866000 227system.cpu.dcache.overall_mshr_miss_latency::total 8866000 |
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| 404system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 | 408system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 |
| 405system.cpu.l2cache.overall_avg_miss_latency::total 60501.179245 | 409system.cpu.l2cache.overall_avg_miss_latency::total 60501.344086 |
| 406system.cpu.l2cache.blocked_cycles::no_mshrs 0 407system.cpu.l2cache.blocked_cycles::no_targets 0 408system.cpu.l2cache.blocked::no_mshrs 0 409system.cpu.l2cache.blocked::no_targets 0 410system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan 411system.cpu.l2cache.avg_blocked_cycles::no_targets nan 412system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 82 413system.cpu.l2cache.ReadExReq_mshr_misses::total 82 | 410system.cpu.l2cache.blocked_cycles::no_mshrs 0 411system.cpu.l2cache.blocked_cycles::no_targets 0 412system.cpu.l2cache.blocked::no_mshrs 0 413system.cpu.l2cache.blocked::no_targets 0 414system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan 415system.cpu.l2cache.avg_blocked_cycles::no_targets nan 416system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 82 417system.cpu.l2cache.ReadExReq_mshr_misses::total 82 |
| 414system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 279 415system.cpu.l2cache.ReadCleanReq_mshr_misses::total 279 416system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 63 417system.cpu.l2cache.ReadSharedReq_mshr_misses::total 63 418system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 419system.cpu.l2cache.demand_mshr_misses::cpu.data 145 420system.cpu.l2cache.demand_mshr_misses::total 424 421system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 422system.cpu.l2cache.overall_mshr_misses::cpu.data 145 423system.cpu.l2cache.overall_mshr_misses::total 424 | 418system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 228 419system.cpu.l2cache.ReadCleanReq_mshr_misses::total 228 420system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 421system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 422system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 423system.cpu.l2cache.demand_mshr_misses::cpu.data 144 424system.cpu.l2cache.demand_mshr_misses::total 372 425system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 426system.cpu.l2cache.overall_mshr_misses::cpu.data 144 427system.cpu.l2cache.overall_mshr_misses::total 372 |
| 424system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4141000 425system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4141000 | 428system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4141000 429system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4141000 |
| 426system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14090000 427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14090000 428system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3181500 429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3181500 430system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14090000 431system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7322500 432system.cpu.l2cache.demand_mshr_miss_latency::total 21412500 433system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14090000 434system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7322500 435system.cpu.l2cache.overall_mshr_miss_latency::total 21412500 | 430system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11514500 431system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11514500 432system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3131000 433system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3131000 434system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11514500 435system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7272000 436system.cpu.l2cache.demand_mshr_miss_latency::total 18786500 437system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11514500 438system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7272000 439system.cpu.l2cache.overall_mshr_miss_latency::total 18786500 |
| 436system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 437system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 438system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 440system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 442system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 443system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 444system.cpu.l2cache.demand_mshr_miss_rate::total 1 445system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 446system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 447system.cpu.l2cache.overall_mshr_miss_rate::total 1 448system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 | 440system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 441system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 442system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 443system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 444system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 445system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 446system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 447system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 448system.cpu.l2cache.demand_mshr_miss_rate::total 1 449system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 450system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 451system.cpu.l2cache.overall_mshr_miss_rate::total 1 452system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 453system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 |
| 450system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.792115 451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.792115 | 454system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.192982 455system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.192982 |
| 452system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 | 456system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 457system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 |
| 454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.792115 | 458system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.192982 |
| 455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 | 459system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 |
| 456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.179245 457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.792115 | 460system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.344086 461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.192982 |
| 458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 | 462system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 |
| 459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.179245 460system.cpu.toL2Bus.snoop_filter.tot_requests 424 | 463system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.344086 464system.cpu.toL2Bus.snoop_filter.tot_requests 372 |
| 461system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 462system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 463system.cpu.toL2Bus.snoop_filter.tot_snoops 0 464system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 465system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 | 465system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 466system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 467system.cpu.toL2Bus.snoop_filter.tot_snoops 0 468system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 469system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| 466system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34045500 467system.cpu.toL2Bus.trans_dist::ReadResp 342 | 470system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31821500 471system.cpu.toL2Bus.trans_dist::ReadResp 290 |
| 468system.cpu.toL2Bus.trans_dist::ReadExReq 82 469system.cpu.toL2Bus.trans_dist::ReadExResp 82 | 472system.cpu.toL2Bus.trans_dist::ReadExReq 82 473system.cpu.toL2Bus.trans_dist::ReadExResp 82 |
| 470system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 471system.cpu.toL2Bus.trans_dist::ReadSharedReq 63 472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 290 474system.cpu.toL2Bus.pkt_count::total 848 475system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 476system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9280 477system.cpu.toL2Bus.pkt_size::total 27136 | 474system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 475system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 478system.cpu.toL2Bus.pkt_count::total 744 479system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 481system.cpu.toL2Bus.pkt_size::total 23808 |
| 478system.cpu.toL2Bus.snoops 0 479system.cpu.toL2Bus.snoopTraffic 0 | 482system.cpu.toL2Bus.snoops 0 483system.cpu.toL2Bus.snoopTraffic 0 |
| 480system.cpu.toL2Bus.snoop_fanout::samples 424 | 484system.cpu.toL2Bus.snoop_fanout::samples 372 |
| 481system.cpu.toL2Bus.snoop_fanout::mean 0 482system.cpu.toL2Bus.snoop_fanout::stdev 0 483system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% | 485system.cpu.toL2Bus.snoop_fanout::mean 0 486system.cpu.toL2Bus.snoop_fanout::stdev 0 487system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| 484system.cpu.toL2Bus.snoop_fanout::0 424 100.00% 100.00% | 488system.cpu.toL2Bus.snoop_fanout::0 372 100.00% 100.00% |
| 485system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% 486system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% 487system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 488system.cpu.toL2Bus.snoop_fanout::min_value 0 489system.cpu.toL2Bus.snoop_fanout::max_value 0 | 489system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% 490system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% 491system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 492system.cpu.toL2Bus.snoop_fanout::min_value 0 493system.cpu.toL2Bus.snoop_fanout::max_value 0 |
| 490system.cpu.toL2Bus.snoop_fanout::total 424 491system.cpu.toL2Bus.reqLayer0.occupancy 212000 | 494system.cpu.toL2Bus.snoop_fanout::total 372 495system.cpu.toL2Bus.reqLayer0.occupancy 186000 |
| 492system.cpu.toL2Bus.reqLayer0.utilization 0.6 | 496system.cpu.toL2Bus.reqLayer0.utilization 0.6 |
| 493system.cpu.toL2Bus.respLayer0.occupancy 418500 494system.cpu.toL2Bus.respLayer0.utilization 1.2 495system.cpu.toL2Bus.respLayer1.occupancy 217500 496system.cpu.toL2Bus.respLayer1.utilization 0.6 497system.membus.snoop_filter.tot_requests 424 | 497system.cpu.toL2Bus.respLayer0.occupancy 342000 498system.cpu.toL2Bus.respLayer0.utilization 1.1 499system.cpu.toL2Bus.respLayer1.occupancy 216000 500system.cpu.toL2Bus.respLayer1.utilization 0.7 501system.membus.snoop_filter.tot_requests 372 |
| 498system.membus.snoop_filter.hit_single_requests 0 499system.membus.snoop_filter.hit_multi_requests 0 500system.membus.snoop_filter.tot_snoops 0 501system.membus.snoop_filter.hit_single_snoops 0 502system.membus.snoop_filter.hit_multi_snoops 0 | 502system.membus.snoop_filter.hit_single_requests 0 503system.membus.snoop_filter.hit_multi_requests 0 504system.membus.snoop_filter.tot_snoops 0 505system.membus.snoop_filter.hit_single_snoops 0 506system.membus.snoop_filter.hit_multi_snoops 0 |
| 503system.membus.pwrStateResidencyTicks::UNDEFINED 34045500 504system.membus.trans_dist::ReadResp 342 | 507system.membus.pwrStateResidencyTicks::UNDEFINED 31821500 508system.membus.trans_dist::ReadResp 290 |
| 505system.membus.trans_dist::ReadExReq 82 506system.membus.trans_dist::ReadExResp 82 | 509system.membus.trans_dist::ReadExReq 82 510system.membus.trans_dist::ReadExResp 82 |
| 507system.membus.trans_dist::ReadSharedReq 342 508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 848 509system.membus.pkt_count::total 848 510system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27136 511system.membus.pkt_size::total 27136 | 511system.membus.trans_dist::ReadSharedReq 290 512system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 744 513system.membus.pkt_count::total 744 514system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23808 515system.membus.pkt_size::total 23808 |
| 512system.membus.snoops 0 513system.membus.snoopTraffic 0 | 516system.membus.snoops 0 517system.membus.snoopTraffic 0 |
| 514system.membus.snoop_fanout::samples 424 | 518system.membus.snoop_fanout::samples 372 |
| 515system.membus.snoop_fanout::mean 0 516system.membus.snoop_fanout::stdev 0 517system.membus.snoop_fanout::underflows 0 0.00% 0.00% | 519system.membus.snoop_fanout::mean 0 520system.membus.snoop_fanout::stdev 0 521system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| 518system.membus.snoop_fanout::0 424 100.00% 100.00% | 522system.membus.snoop_fanout::0 372 100.00% 100.00% |
| 519system.membus.snoop_fanout::1 0 0.00% 100.00% 520system.membus.snoop_fanout::overflows 0 0.00% 100.00% 521system.membus.snoop_fanout::min_value 0 522system.membus.snoop_fanout::max_value 0 | 523system.membus.snoop_fanout::1 0 0.00% 100.00% 524system.membus.snoop_fanout::overflows 0 0.00% 100.00% 525system.membus.snoop_fanout::min_value 0 526system.membus.snoop_fanout::max_value 0 |
| 523system.membus.snoop_fanout::total 424 524system.membus.reqLayer0.occupancy 424500 | 527system.membus.snoop_fanout::total 372 528system.membus.reqLayer0.occupancy 372500 |
| 525system.membus.reqLayer0.utilization 1.2 | 529system.membus.reqLayer0.utilization 1.2 |
| 526system.membus.respLayer1.occupancy 2120000 527system.membus.respLayer1.utilization 6.2 | 530system.membus.respLayer1.occupancy 1860000 531system.membus.respLayer1.utilization 5.8 |
| 528 529---------- End Simulation Statistics ---------- | 532 533---------- End Simulation Statistics ---------- |