1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {

--- 390 unchanged lines hidden (view full) ---

399 ],
400 "errout": "cerr",
401 "useArchPT": false,
402 "egid": 100,
403 "output": "cout"
404 }
405 ],
406 "name": "cpu",
407 "dtb": {
408 "name": "dtb",
409 "eventq_index": 0,
410 "cxx_class": "RiscvISA::TLB",
411 "path": "system.cpu.dtb",
412 "type": "RiscvTLB",
413 "size": 64
414 },

--- 96 unchanged lines hidden ---