1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "membus": { --- 230 unchanged lines hidden (view full) --- 239 ], 240 "errout": "cerr", 241 "useArchPT": false, 242 "egid": 100, 243 "output": "cout" 244 } 245 ], 246 "name": "cpu", |
247 "wait_for_remote_gdb": false, |
248 "dtb": { 249 "name": "dtb", 250 "eventq_index": 0, 251 "cxx_class": "RiscvISA::TLB", 252 "path": "system.cpu.dtb", 253 "type": "RiscvTLB", 254 "size": 64 255 }, --- 37 unchanged lines hidden --- |