3sim_seconds 0.000008 # Number of seconds simulated
4sim_ticks 7939500 # Number of ticks simulated
5final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 81718 # Simulator instruction rate (inst/s)
8host_op_rate 81674 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 408398393 # Simulator tick rate (ticks/s)
10host_mem_usage 251348 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 1587 # Number of instructions simulated
13sim_ops 1587 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory
19system.physmem.bytes_read::total 11648 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 182 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 184 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 11776 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 93 # Per bank write bursts
46system.physmem.perBankRdBursts::1 62 # Per bank write bursts
47system.physmem.perBankRdBursts::2 18 # Per bank write bursts
48system.physmem.perBankRdBursts::3 9 # Per bank write bursts
49system.physmem.perBankRdBursts::4 0 # Per bank write bursts
50system.physmem.perBankRdBursts::5 0 # Per bank write bursts
51system.physmem.perBankRdBursts::6 0 # Per bank write bursts
52system.physmem.perBankRdBursts::7 0 # Per bank write bursts
53system.physmem.perBankRdBursts::8 0 # Per bank write bursts
54system.physmem.perBankRdBursts::9 0 # Per bank write bursts
55system.physmem.perBankRdBursts::10 0 # Per bank write bursts
56system.physmem.perBankRdBursts::11 0 # Per bank write bursts
57system.physmem.perBankRdBursts::12 0 # Per bank write bursts
58system.physmem.perBankRdBursts::13 0 # Per bank write bursts
59system.physmem.perBankRdBursts::14 0 # Per bank write bursts
60system.physmem.perBankRdBursts::15 0 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 7854500 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 184 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation
200system.physmem.totQLat 1405000 # Total ticks spent queuing
201system.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM
202system.physmem.totBusLat 910000 # Total ticks spent in databus transfers
203system.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst
204system.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst
205system.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst
206system.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s
207system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
208system.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s
209system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
210system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
211system.physmem.busUtil 11.46 # Data bus utilization in percentage
212system.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads
213system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
214system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing
215system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
216system.physmem.readRowHits 169 # Number of row buffer hits during reads
217system.physmem.writeRowHits 0 # Number of row buffer hits during writes
218system.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads
219system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
220system.physmem.avgGap 42687.50 # Average gap between requests
221system.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined
222system.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ)
223system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ)
224system.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ)
225system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
226system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
227system.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ)
228system.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ)
229system.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ)
230system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
231system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
232system.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ)
233system.physmem_0.averagePower 711.322044 # Core power per rank (mW)
234system.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank
235system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
236system.physmem_0.memoryStateTime::REF 139500 # Time in different power states
237system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
238system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
239system.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states
240system.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states
241system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ)
242system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
243system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ)
244system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
245system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
246system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ)
247system.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ)
248system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
249system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
250system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
251system.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ)
252system.physmem_1.averagePower 462.726424 # Core power per rank (mW)
253system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
254system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states
255system.physmem_1.memoryStateTime::REF 153250 # Time in different power states
256system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
257system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
258system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
259system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
260system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
261system.cpu.branchPred.lookups 1255 # Number of BP lookups
262system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted
263system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect
264system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups
265system.cpu.branchPred.BTBHits 302 # Number of BTB hits
266system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
267system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage
268system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
269system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
270system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups.
271system.cpu.branchPred.indirectHits 24 # Number of indirect target hits.
272system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
273system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches.
274system.cpu_clk_domain.clock 500 # Clock period in ticks
275system.cpu.dtb.read_hits 0 # DTB read hits
276system.cpu.dtb.read_misses 0 # DTB read misses
277system.cpu.dtb.read_accesses 0 # DTB read accesses
278system.cpu.dtb.write_hits 0 # DTB write hits
279system.cpu.dtb.write_misses 0 # DTB write misses
280system.cpu.dtb.write_accesses 0 # DTB write accesses
281system.cpu.dtb.hits 0 # DTB hits
282system.cpu.dtb.misses 0 # DTB misses
283system.cpu.dtb.accesses 0 # DTB accesses
284system.cpu.itb.read_hits 0 # DTB read hits
285system.cpu.itb.read_misses 0 # DTB read misses
286system.cpu.itb.read_accesses 0 # DTB read accesses
287system.cpu.itb.write_hits 0 # DTB write hits
288system.cpu.itb.write_misses 0 # DTB write misses
289system.cpu.itb.write_accesses 0 # DTB write accesses
290system.cpu.itb.hits 0 # DTB hits
291system.cpu.itb.misses 0 # DTB misses
292system.cpu.itb.accesses 0 # DTB accesses
293system.cpu.workload.numSyscalls 9 # Number of system calls
294system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states
295system.cpu.numCycles 15880 # number of cpu cycles simulated
296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
298system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss
299system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed
300system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered
301system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken
302system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked
303system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing
304system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
305system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps
306system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR
307system.cpu.fetch.CacheLines 803 # Number of cache lines fetched
308system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed
309system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total)
312system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
313system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total)
314system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total)
315system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total)
316system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total)
317system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total)
318system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total)
319system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total)
320system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total)
321system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total)
322system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
323system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
324system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
325system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle
327system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle
328system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle
329system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked
330system.cpu.decode.RunCycles 756 # Number of cycles decode is running
331system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
332system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing
333system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch
334system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
335system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode
336system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode
337system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing
338system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle
339system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking
340system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst
341system.cpu.rename.RunCycles 673 # Number of cycles rename is running
342system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking
343system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename
344system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full
345system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed
346system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made
347system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups
348system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed
349system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing
350system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
351system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed
352system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer
353system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit.
354system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
355system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
356system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
357system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec)
358system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
359system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued
360system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
361system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling
362system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph
363system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
364system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle
372system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle
373system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle
374system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle
375system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle
376system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle
377system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
378system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
379system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
380system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle
381system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
382system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available
383system.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available
384system.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available
385system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available
386system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available
387system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available
388system.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available
389system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available
390system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available
391system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available
392system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available
393system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available
394system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available
395system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available
396system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available
397system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available
402system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available
403system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available
404system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available
405system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available
406system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available
407system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available
408system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available
409system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available
410system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available
413system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available
414system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
417system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
418system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
419system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued
420system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued
421system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued
422system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued
423system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued
424system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued
425system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued
426system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued
427system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued
428system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued
429system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued
430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued
436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued
437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued
438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued
439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued
440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued
441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued
442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued
443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued
444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued
445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued
446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued
447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued
451system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued
452system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
455system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
456system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
457system.cpu.iq.FU_type_0::total 2703 # Type of FU issued
458system.cpu.iq.rate 0.170214 # Inst issue rate
459system.cpu.iq.fu_busy_cnt 70 # FU busy when requested
460system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst)
461system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads
462system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes
463system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses
464system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
465system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
466system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
467system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses
468system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
469system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores
470system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
471system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed
472system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
473system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations
474system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed
475system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
476system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
477system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
478system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
479system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
480system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing
481system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking
482system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
483system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ
484system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch
485system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions
486system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
487system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions
488system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
489system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
490system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations
491system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly
492system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly
493system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute
494system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions
495system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed
496system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute
497system.cpu.iew.exec_swp 0 # number of swp insts executed
498system.cpu.iew.exec_nop 0 # number of nop insts executed
499system.cpu.iew.exec_refs 846 # number of memory reference insts executed
500system.cpu.iew.exec_branches 566 # Number of branches executed
501system.cpu.iew.exec_stores 375 # Number of stores executed
502system.cpu.iew.exec_rate 0.154849 # Inst execution rate
503system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit
504system.cpu.iew.wb_count 2318 # cumulative count of insts written-back
505system.cpu.iew.wb_producers 798 # num instructions producing a value
506system.cpu.iew.wb_consumers 1140 # num instructions consuming a value
507system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle
508system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back
509system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit
510system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
511system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted
512system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle
513system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle
514system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle
515system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
516system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle
517system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle
518system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle
519system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle
520system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle
521system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle
522system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle
523system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle
524system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle
525system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
526system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
527system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
528system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle
529system.cpu.commit.committedInsts 1587 # Number of instructions committed
530system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed
531system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
532system.cpu.commit.refs 568 # Number of memory references committed
533system.cpu.commit.loads 289 # Number of loads committed
534system.cpu.commit.membars 0 # Number of memory barriers committed
535system.cpu.commit.branches 373 # Number of branches committed
536system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
537system.cpu.commit.int_insts 1587 # Number of committed integer instructions.
538system.cpu.commit.function_calls 142 # Number of function calls committed.
539system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
540system.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction
541system.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction
542system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction
543system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction
544system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction
545system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction
546system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction
547system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction
548system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction
549system.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction
550system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction
552system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction
553system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction
554system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction
555system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction
556system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction
557system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction
558system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction
559system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction
560system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction
561system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction
562system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction
563system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction
564system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction
565system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction
566system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction
567system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction
568system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction
569system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction
570system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction
571system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction
572system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction
573system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
574system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
575system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
576system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
577system.cpu.commit.op_class_0::total 1587 # Class of committed instruction
578system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached
579system.cpu.rob.rob_reads 7050 # The number of ROB reads
580system.cpu.rob.rob_writes 6361 # The number of ROB writes
581system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself
582system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling
583system.cpu.committedInsts 1587 # Number of Instructions Simulated
584system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated
585system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction
586system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads
587system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle
588system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads
589system.cpu.int_regfile_reads 3116 # number of integer regfile reads
590system.cpu.int_regfile_writes 1668 # number of integer regfile writes
591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
592system.cpu.dcache.tags.replacements 0 # number of replacements
593system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use
594system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks.
595system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
596system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks.
597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
598system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor
599system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy
600system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy
601system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
602system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
603system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
604system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses
605system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses
606system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
607system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits
608system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits
609system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits
610system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits
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612system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits
613system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits
614system.cpu.dcache.overall_hits::total 625 # number of overall hits
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616system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses
617system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
618system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
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620system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses
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622system.cpu.dcache.overall_misses::total 106 # number of overall misses
623system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles
624system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles
625system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles
626system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles
627system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles
628system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles
629system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles
630system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles
631system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses)
632system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses)
633system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
634system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
635system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses
636system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses
637system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses
638system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses
639system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses
640system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses
641system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses
642system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses
643system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses
644system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses
645system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses
646system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses
647system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency
648system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency
649system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency
650system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency
651system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency
652system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency
653system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency
654system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency
655system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
656system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
657system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
658system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
659system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
660system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
661system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
662system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
663system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits
664system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits
665system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits
666system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
667system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits
668system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits
669system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses
670system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses
671system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses
672system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses
673system.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses
674system.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses
675system.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses
676system.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses
677system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles
678system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles
679system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles
680system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles
681system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles
682system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles
683system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles
684system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles
685system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses
686system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
687system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses
688system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses
689system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses
690system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses
691system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses
692system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses
693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency
694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency
695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency
696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency
697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency
698system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency
699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency
700system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency
701system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
702system.cpu.icache.tags.replacements 0 # number of replacements
703system.cpu.icache.tags.tagsinuse 76.387250 # Cycle average of tags in use
704system.cpu.icache.tags.total_refs 579 # Total number of references to valid blocks.
705system.cpu.icache.tags.sampled_refs 151 # Sample count of references to valid blocks.
706system.cpu.icache.tags.avg_refs 3.834437 # Average number of references to valid blocks.
707system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
708system.cpu.icache.tags.occ_blocks::cpu.inst 76.387250 # Average occupied blocks per requestor
709system.cpu.icache.tags.occ_percent::cpu.inst 0.037298 # Average percentage of cache occupancy
710system.cpu.icache.tags.occ_percent::total 0.037298 # Average percentage of cache occupancy
711system.cpu.icache.tags.occ_task_id_blocks::1024 151 # Occupied blocks per task id
712system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
713system.cpu.icache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
714system.cpu.icache.tags.tag_accesses 1753 # Number of tag accesses
715system.cpu.icache.tags.data_accesses 1753 # Number of data accesses
716system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
717system.cpu.icache.ReadReq_hits::cpu.inst 579 # number of ReadReq hits
718system.cpu.icache.ReadReq_hits::total 579 # number of ReadReq hits
719system.cpu.icache.demand_hits::cpu.inst 579 # number of demand (read+write) hits
720system.cpu.icache.demand_hits::total 579 # number of demand (read+write) hits
721system.cpu.icache.overall_hits::cpu.inst 579 # number of overall hits
722system.cpu.icache.overall_hits::total 579 # number of overall hits
723system.cpu.icache.ReadReq_misses::cpu.inst 222 # number of ReadReq misses
724system.cpu.icache.ReadReq_misses::total 222 # number of ReadReq misses
725system.cpu.icache.demand_misses::cpu.inst 222 # number of demand (read+write) misses
726system.cpu.icache.demand_misses::total 222 # number of demand (read+write) misses
727system.cpu.icache.overall_misses::cpu.inst 222 # number of overall misses
728system.cpu.icache.overall_misses::total 222 # number of overall misses
729system.cpu.icache.ReadReq_miss_latency::cpu.inst 16076000 # number of ReadReq miss cycles
730system.cpu.icache.ReadReq_miss_latency::total 16076000 # number of ReadReq miss cycles
731system.cpu.icache.demand_miss_latency::cpu.inst 16076000 # number of demand (read+write) miss cycles
732system.cpu.icache.demand_miss_latency::total 16076000 # number of demand (read+write) miss cycles
733system.cpu.icache.overall_miss_latency::cpu.inst 16076000 # number of overall miss cycles
734system.cpu.icache.overall_miss_latency::total 16076000 # number of overall miss cycles
735system.cpu.icache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses)
736system.cpu.icache.ReadReq_accesses::total 801 # number of ReadReq accesses(hits+misses)
737system.cpu.icache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
738system.cpu.icache.demand_accesses::total 801 # number of demand (read+write) accesses
739system.cpu.icache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
740system.cpu.icache.overall_accesses::total 801 # number of overall (read+write) accesses
741system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.277154 # miss rate for ReadReq accesses
742system.cpu.icache.ReadReq_miss_rate::total 0.277154 # miss rate for ReadReq accesses
743system.cpu.icache.demand_miss_rate::cpu.inst 0.277154 # miss rate for demand accesses
744system.cpu.icache.demand_miss_rate::total 0.277154 # miss rate for demand accesses
745system.cpu.icache.overall_miss_rate::cpu.inst 0.277154 # miss rate for overall accesses
746system.cpu.icache.overall_miss_rate::total 0.277154 # miss rate for overall accesses
747system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72414.414414 # average ReadReq miss latency
748system.cpu.icache.ReadReq_avg_miss_latency::total 72414.414414 # average ReadReq miss latency
749system.cpu.icache.demand_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency
750system.cpu.icache.demand_avg_miss_latency::total 72414.414414 # average overall miss latency
751system.cpu.icache.overall_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency
752system.cpu.icache.overall_avg_miss_latency::total 72414.414414 # average overall miss latency
753system.cpu.icache.blocked_cycles::no_mshrs 447 # number of cycles access was blocked
754system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
755system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
756system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
757system.cpu.icache.avg_blocked_cycles::no_mshrs 89.400000 # average number of cycles each access was blocked
758system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
759system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
760system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
761system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
762system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
763system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
764system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153 # number of ReadReq MSHR misses
766system.cpu.icache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses
767system.cpu.icache.demand_mshr_misses::cpu.inst 153 # number of demand (read+write) MSHR misses
768system.cpu.icache.demand_mshr_misses::total 153 # number of demand (read+write) MSHR misses
769system.cpu.icache.overall_mshr_misses::cpu.inst 153 # number of overall MSHR misses
770system.cpu.icache.overall_mshr_misses::total 153 # number of overall MSHR misses
771system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11858500 # number of ReadReq MSHR miss cycles
772system.cpu.icache.ReadReq_mshr_miss_latency::total 11858500 # number of ReadReq MSHR miss cycles
773system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11858500 # number of demand (read+write) MSHR miss cycles
774system.cpu.icache.demand_mshr_miss_latency::total 11858500 # number of demand (read+write) MSHR miss cycles
775system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11858500 # number of overall MSHR miss cycles
776system.cpu.icache.overall_mshr_miss_latency::total 11858500 # number of overall MSHR miss cycles
777system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for ReadReq accesses
778system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191011 # mshr miss rate for ReadReq accesses
779system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for demand accesses
780system.cpu.icache.demand_mshr_miss_rate::total 0.191011 # mshr miss rate for demand accesses
781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for overall accesses
782system.cpu.icache.overall_mshr_miss_rate::total 0.191011 # mshr miss rate for overall accesses
783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77506.535948 # average ReadReq mshr miss latency
784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77506.535948 # average ReadReq mshr miss latency
785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency
786system.cpu.icache.demand_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency
787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency
788system.cpu.icache.overall_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency
789system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
790system.cpu.l2cache.tags.replacements 0 # number of replacements
791system.cpu.l2cache.tags.tagsinuse 99.069725 # Cycle average of tags in use
792system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
793system.cpu.l2cache.tags.sampled_refs 182 # Sample count of references to valid blocks.
794system.cpu.l2cache.tags.avg_refs 0.010989 # Average number of references to valid blocks.
795system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
796system.cpu.l2cache.tags.occ_blocks::cpu.inst 75.716364 # Average occupied blocks per requestor
797system.cpu.l2cache.tags.occ_blocks::cpu.data 23.353361 # Average occupied blocks per requestor
798system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002311 # Average percentage of cache occupancy
799system.cpu.l2cache.tags.occ_percent::cpu.data 0.000713 # Average percentage of cache occupancy
800system.cpu.l2cache.tags.occ_percent::total 0.003023 # Average percentage of cache occupancy
801system.cpu.l2cache.tags.occ_task_id_blocks::1024 182 # Occupied blocks per task id
802system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
803system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005554 # Percentage of cache occupancy per task id
804system.cpu.l2cache.tags.tag_accesses 1678 # Number of tag accesses
805system.cpu.l2cache.tags.data_accesses 1678 # Number of data accesses
806system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
807system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
808system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
809system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
810system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
811system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
812system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
813system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
814system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
815system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
816system.cpu.l2cache.overall_hits::total 2 # number of overall hits
817system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses
818system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses
819system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 152 # number of ReadCleanReq misses
820system.cpu.l2cache.ReadCleanReq_misses::total 152 # number of ReadCleanReq misses
821system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses
822system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses
823system.cpu.l2cache.demand_misses::cpu.inst 152 # number of demand (read+write) misses
824system.cpu.l2cache.demand_misses::cpu.data 33 # number of demand (read+write) misses
825system.cpu.l2cache.demand_misses::total 185 # number of demand (read+write) misses
826system.cpu.l2cache.overall_misses::cpu.inst 152 # number of overall misses
827system.cpu.l2cache.overall_misses::cpu.data 33 # number of overall misses
828system.cpu.l2cache.overall_misses::total 185 # number of overall misses
829system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404500 # number of ReadExReq miss cycles
830system.cpu.l2cache.ReadExReq_miss_latency::total 1404500 # number of ReadExReq miss cycles
831system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11620000 # number of ReadCleanReq miss cycles
832system.cpu.l2cache.ReadCleanReq_miss_latency::total 11620000 # number of ReadCleanReq miss cycles
833system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1106000 # number of ReadSharedReq miss cycles
834system.cpu.l2cache.ReadSharedReq_miss_latency::total 1106000 # number of ReadSharedReq miss cycles
835system.cpu.l2cache.demand_miss_latency::cpu.inst 11620000 # number of demand (read+write) miss cycles
836system.cpu.l2cache.demand_miss_latency::cpu.data 2510500 # number of demand (read+write) miss cycles
837system.cpu.l2cache.demand_miss_latency::total 14130500 # number of demand (read+write) miss cycles
838system.cpu.l2cache.overall_miss_latency::cpu.inst 11620000 # number of overall miss cycles
839system.cpu.l2cache.overall_miss_latency::cpu.data 2510500 # number of overall miss cycles
840system.cpu.l2cache.overall_miss_latency::total 14130500 # number of overall miss cycles
841system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses)
842system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses)
843system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 153 # number of ReadCleanReq accesses(hits+misses)
844system.cpu.l2cache.ReadCleanReq_accesses::total 153 # number of ReadCleanReq accesses(hits+misses)
845system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses)
846system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses)
847system.cpu.l2cache.demand_accesses::cpu.inst 153 # number of demand (read+write) accesses
848system.cpu.l2cache.demand_accesses::cpu.data 34 # number of demand (read+write) accesses
849system.cpu.l2cache.demand_accesses::total 187 # number of demand (read+write) accesses
850system.cpu.l2cache.overall_accesses::cpu.inst 153 # number of overall (read+write) accesses
851system.cpu.l2cache.overall_accesses::cpu.data 34 # number of overall (read+write) accesses
852system.cpu.l2cache.overall_accesses::total 187 # number of overall (read+write) accesses
853system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
854system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
855system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993464 # miss rate for ReadCleanReq accesses
856system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993464 # miss rate for ReadCleanReq accesses
857system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses
858system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses
859system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993464 # miss rate for demand accesses
860system.cpu.l2cache.demand_miss_rate::cpu.data 0.970588 # miss rate for demand accesses
861system.cpu.l2cache.demand_miss_rate::total 0.989305 # miss rate for demand accesses
862system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993464 # miss rate for overall accesses
863system.cpu.l2cache.overall_miss_rate::cpu.data 0.970588 # miss rate for overall accesses
864system.cpu.l2cache.overall_miss_rate::total 0.989305 # miss rate for overall accesses
865system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78027.777778 # average ReadExReq miss latency
866system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78027.777778 # average ReadExReq miss latency
867system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76447.368421 # average ReadCleanReq miss latency
868system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76447.368421 # average ReadCleanReq miss latency
869system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73733.333333 # average ReadSharedReq miss latency
870system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73733.333333 # average ReadSharedReq miss latency
871system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency
872system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency
873system.cpu.l2cache.demand_avg_miss_latency::total 76381.081081 # average overall miss latency
874system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency
875system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency
876system.cpu.l2cache.overall_avg_miss_latency::total 76381.081081 # average overall miss latency
877system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
878system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
879system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
880system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
881system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
882system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
883system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses
884system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses
885system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 152 # number of ReadCleanReq MSHR misses
886system.cpu.l2cache.ReadCleanReq_mshr_misses::total 152 # number of ReadCleanReq MSHR misses
887system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses
888system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses
889system.cpu.l2cache.demand_mshr_misses::cpu.inst 152 # number of demand (read+write) MSHR misses
890system.cpu.l2cache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses
891system.cpu.l2cache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses
892system.cpu.l2cache.overall_mshr_misses::cpu.inst 152 # number of overall MSHR misses
893system.cpu.l2cache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses
894system.cpu.l2cache.overall_mshr_misses::total 185 # number of overall MSHR misses
895system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1224500 # number of ReadExReq MSHR miss cycles
896system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1224500 # number of ReadExReq MSHR miss cycles
897system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10120000 # number of ReadCleanReq MSHR miss cycles
898system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10120000 # number of ReadCleanReq MSHR miss cycles
899system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 966000 # number of ReadSharedReq MSHR miss cycles
900system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 966000 # number of ReadSharedReq MSHR miss cycles
901system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10120000 # number of demand (read+write) MSHR miss cycles
902system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2190500 # number of demand (read+write) MSHR miss cycles
903system.cpu.l2cache.demand_mshr_miss_latency::total 12310500 # number of demand (read+write) MSHR miss cycles
904system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10120000 # number of overall MSHR miss cycles
905system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2190500 # number of overall MSHR miss cycles
906system.cpu.l2cache.overall_mshr_miss_latency::total 12310500 # number of overall MSHR miss cycles
907system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
908system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
909system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for ReadCleanReq accesses
910system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993464 # mshr miss rate for ReadCleanReq accesses
911system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses
912system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses
913system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for demand accesses
914system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for demand accesses
915system.cpu.l2cache.demand_mshr_miss_rate::total 0.989305 # mshr miss rate for demand accesses
916system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for overall accesses
917system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for overall accesses
918system.cpu.l2cache.overall_mshr_miss_rate::total 0.989305 # mshr miss rate for overall accesses
919system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency
920system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency
921system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency
922system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency
923system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency
924system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency
925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency
926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency
927system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency
928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency
929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency
930system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency
931system.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter.
932system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
933system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
934system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
935system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
936system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
937system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
938system.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution
939system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution
940system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution
941system.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution
942system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution
943system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes)
944system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes)
945system.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes)
946system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes)
947system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes)
948system.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes)
949system.cpu.toL2Bus.snoops 0 # Total snoops (count)
950system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
951system.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram
952system.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram
953system.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram
954system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
955system.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram
956system.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram
957system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
958system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
959system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
960system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
961system.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram
962system.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks)
963system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
964system.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks)
965system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
966system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks)
967system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
968system.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter.
969system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
970system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
971system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
972system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
973system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
974system.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
975system.membus.trans_dist::ReadResp 164 # Transaction distribution
976system.membus.trans_dist::ReadExReq 18 # Transaction distribution
977system.membus.trans_dist::ReadExResp 18 # Transaction distribution
978system.membus.trans_dist::ReadSharedReq 166 # Transaction distribution
979system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes)
980system.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes)
981system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes)
982system.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes)
983system.membus.snoops 0 # Total snoops (count)
984system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
985system.membus.snoop_fanout::samples 184 # Request fanout histogram
986system.membus.snoop_fanout::mean 0 # Request fanout histogram
987system.membus.snoop_fanout::stdev 0 # Request fanout histogram
988system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
989system.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram
990system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
991system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
992system.membus.snoop_fanout::min_value 0 # Request fanout histogram
993system.membus.snoop_fanout::max_value 0 # Request fanout histogram
994system.membus.snoop_fanout::total 184 # Request fanout histogram
995system.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
996system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
997system.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks)
998system.membus.respLayer1.utilization 11.9 # Layer utilization (%)
| 3sim_seconds 0.000022
4sim_ticks 21876000
5final_tick 21876000
6sim_freq 1000000000000
7host_inst_rate 17054
8host_op_rate 17078
9host_tick_rate 67215440
10host_mem_usage 279228
11host_seconds 0.33
12sim_insts 5550
13sim_ops 5558
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 21876000
17system.physmem.bytes_read::cpu.inst 25344
18system.physmem.bytes_read::cpu.data 9856
19system.physmem.bytes_read::total 35200
20system.physmem.bytes_inst_read::cpu.inst 25344
21system.physmem.bytes_inst_read::total 25344
22system.physmem.num_reads::cpu.inst 396
23system.physmem.num_reads::cpu.data 154
24system.physmem.num_reads::total 550
25system.physmem.bw_read::cpu.inst 1158529896
26system.physmem.bw_read::cpu.data 450539404
27system.physmem.bw_read::total 1609069300
28system.physmem.bw_inst_read::cpu.inst 1158529896
29system.physmem.bw_inst_read::total 1158529896
30system.physmem.bw_total::cpu.inst 1158529896
31system.physmem.bw_total::cpu.data 450539404
32system.physmem.bw_total::total 1609069300
33system.physmem.readReqs 550
34system.physmem.writeReqs 0
35system.physmem.readBursts 550
36system.physmem.writeBursts 0
37system.physmem.bytesReadDRAM 35200
38system.physmem.bytesReadWrQ 0
39system.physmem.bytesWritten 0
40system.physmem.bytesReadSys 35200
41system.physmem.bytesWrittenSys 0
42system.physmem.servicedByWrQ 0
43system.physmem.mergedWrBursts 0
44system.physmem.neitherReadNorWriteReqs 0
45system.physmem.perBankRdBursts::0 59
46system.physmem.perBankRdBursts::1 84
47system.physmem.perBankRdBursts::2 53
48system.physmem.perBankRdBursts::3 46
49system.physmem.perBankRdBursts::4 34
50system.physmem.perBankRdBursts::5 35
51system.physmem.perBankRdBursts::6 43
52system.physmem.perBankRdBursts::7 24
53system.physmem.perBankRdBursts::8 33
54system.physmem.perBankRdBursts::9 29
55system.physmem.perBankRdBursts::10 23
56system.physmem.perBankRdBursts::11 18
57system.physmem.perBankRdBursts::12 51
58system.physmem.perBankRdBursts::13 5
59system.physmem.perBankRdBursts::14 6
60system.physmem.perBankRdBursts::15 7
61system.physmem.perBankWrBursts::0 0
62system.physmem.perBankWrBursts::1 0
63system.physmem.perBankWrBursts::2 0
64system.physmem.perBankWrBursts::3 0
65system.physmem.perBankWrBursts::4 0
66system.physmem.perBankWrBursts::5 0
67system.physmem.perBankWrBursts::6 0
68system.physmem.perBankWrBursts::7 0
69system.physmem.perBankWrBursts::8 0
70system.physmem.perBankWrBursts::9 0
71system.physmem.perBankWrBursts::10 0
72system.physmem.perBankWrBursts::11 0
73system.physmem.perBankWrBursts::12 0
74system.physmem.perBankWrBursts::13 0
75system.physmem.perBankWrBursts::14 0
76system.physmem.perBankWrBursts::15 0
77system.physmem.numRdRetry 0
78system.physmem.numWrRetry 0
79system.physmem.totGap 21770000
80system.physmem.readPktSize::0 0
81system.physmem.readPktSize::1 0
82system.physmem.readPktSize::2 0
83system.physmem.readPktSize::3 0
84system.physmem.readPktSize::4 0
85system.physmem.readPktSize::5 0
86system.physmem.readPktSize::6 550
87system.physmem.writePktSize::0 0
88system.physmem.writePktSize::1 0
89system.physmem.writePktSize::2 0
90system.physmem.writePktSize::3 0
91system.physmem.writePktSize::4 0
92system.physmem.writePktSize::5 0
93system.physmem.writePktSize::6 0
94system.physmem.rdQLenPdf::0 249
95system.physmem.rdQLenPdf::1 182
96system.physmem.rdQLenPdf::2 70
97system.physmem.rdQLenPdf::3 35
98system.physmem.rdQLenPdf::4 11
99system.physmem.rdQLenPdf::5 3
100system.physmem.rdQLenPdf::6 0
101system.physmem.rdQLenPdf::7 0
102system.physmem.rdQLenPdf::8 0
103system.physmem.rdQLenPdf::9 0
104system.physmem.rdQLenPdf::10 0
105system.physmem.rdQLenPdf::11 0
106system.physmem.rdQLenPdf::12 0
107system.physmem.rdQLenPdf::13 0
108system.physmem.rdQLenPdf::14 0
109system.physmem.rdQLenPdf::15 0
110system.physmem.rdQLenPdf::16 0
111system.physmem.rdQLenPdf::17 0
112system.physmem.rdQLenPdf::18 0
113system.physmem.rdQLenPdf::19 0
114system.physmem.rdQLenPdf::20 0
115system.physmem.rdQLenPdf::21 0
116system.physmem.rdQLenPdf::22 0
117system.physmem.rdQLenPdf::23 0
118system.physmem.rdQLenPdf::24 0
119system.physmem.rdQLenPdf::25 0
120system.physmem.rdQLenPdf::26 0
121system.physmem.rdQLenPdf::27 0
122system.physmem.rdQLenPdf::28 0
123system.physmem.rdQLenPdf::29 0
124system.physmem.rdQLenPdf::30 0
125system.physmem.rdQLenPdf::31 0
126system.physmem.wrQLenPdf::0 0
127system.physmem.wrQLenPdf::1 0
128system.physmem.wrQLenPdf::2 0
129system.physmem.wrQLenPdf::3 0
130system.physmem.wrQLenPdf::4 0
131system.physmem.wrQLenPdf::5 0
132system.physmem.wrQLenPdf::6 0
133system.physmem.wrQLenPdf::7 0
134system.physmem.wrQLenPdf::8 0
135system.physmem.wrQLenPdf::9 0
136system.physmem.wrQLenPdf::10 0
137system.physmem.wrQLenPdf::11 0
138system.physmem.wrQLenPdf::12 0
139system.physmem.wrQLenPdf::13 0
140system.physmem.wrQLenPdf::14 0
141system.physmem.wrQLenPdf::15 0
142system.physmem.wrQLenPdf::16 0
143system.physmem.wrQLenPdf::17 0
144system.physmem.wrQLenPdf::18 0
145system.physmem.wrQLenPdf::19 0
146system.physmem.wrQLenPdf::20 0
147system.physmem.wrQLenPdf::21 0
148system.physmem.wrQLenPdf::22 0
149system.physmem.wrQLenPdf::23 0
150system.physmem.wrQLenPdf::24 0
151system.physmem.wrQLenPdf::25 0
152system.physmem.wrQLenPdf::26 0
153system.physmem.wrQLenPdf::27 0
154system.physmem.wrQLenPdf::28 0
155system.physmem.wrQLenPdf::29 0
156system.physmem.wrQLenPdf::30 0
157system.physmem.wrQLenPdf::31 0
158system.physmem.wrQLenPdf::32 0
159system.physmem.wrQLenPdf::33 0
160system.physmem.wrQLenPdf::34 0
161system.physmem.wrQLenPdf::35 0
162system.physmem.wrQLenPdf::36 0
163system.physmem.wrQLenPdf::37 0
164system.physmem.wrQLenPdf::38 0
165system.physmem.wrQLenPdf::39 0
166system.physmem.wrQLenPdf::40 0
167system.physmem.wrQLenPdf::41 0
168system.physmem.wrQLenPdf::42 0
169system.physmem.wrQLenPdf::43 0
170system.physmem.wrQLenPdf::44 0
171system.physmem.wrQLenPdf::45 0
172system.physmem.wrQLenPdf::46 0
173system.physmem.wrQLenPdf::47 0
174system.physmem.wrQLenPdf::48 0
175system.physmem.wrQLenPdf::49 0
176system.physmem.wrQLenPdf::50 0
177system.physmem.wrQLenPdf::51 0
178system.physmem.wrQLenPdf::52 0
179system.physmem.wrQLenPdf::53 0
180system.physmem.wrQLenPdf::54 0
181system.physmem.wrQLenPdf::55 0
182system.physmem.wrQLenPdf::56 0
183system.physmem.wrQLenPdf::57 0
184system.physmem.wrQLenPdf::58 0
185system.physmem.wrQLenPdf::59 0
186system.physmem.wrQLenPdf::60 0
187system.physmem.wrQLenPdf::61 0
188system.physmem.wrQLenPdf::62 0
189system.physmem.wrQLenPdf::63 0
190system.physmem.bytesPerActivate::samples 94
191system.physmem.bytesPerActivate::mean 345.191489
192system.physmem.bytesPerActivate::gmean 213.340807
193system.physmem.bytesPerActivate::stdev 332.118818
194system.physmem.bytesPerActivate::0-127 29 30.85% 30.85%
195system.physmem.bytesPerActivate::128-255 21 22.34% 53.19%
196system.physmem.bytesPerActivate::256-383 12 12.77% 65.96%
197system.physmem.bytesPerActivate::384-511 7 7.45% 73.40%
198system.physmem.bytesPerActivate::512-639 6 6.38% 79.79%
199system.physmem.bytesPerActivate::640-767 4 4.26% 84.04%
200system.physmem.bytesPerActivate::768-895 2 2.13% 86.17%
201system.physmem.bytesPerActivate::1024-1151 13 13.83% 100.00%
202system.physmem.bytesPerActivate::total 94
203system.physmem.totQLat 7873000
204system.physmem.totMemAccLat 18185500
205system.physmem.totBusLat 2750000
206system.physmem.avgQLat 14314.55
207system.physmem.avgBusLat 5000.00
208system.physmem.avgMemAccLat 33064.55
209system.physmem.avgRdBW 1609.07
210system.physmem.avgWrBW 0.00
211system.physmem.avgRdBWSys 1609.07
212system.physmem.avgWrBWSys 0.00
213system.physmem.peakBW 12800.00
214system.physmem.busUtil 12.57
215system.physmem.busUtilRead 12.57
216system.physmem.busUtilWrite 0.00
217system.physmem.avgRdQLen 2.14
218system.physmem.avgWrQLen 0.00
219system.physmem.readRowHits 445
220system.physmem.writeRowHits 0
221system.physmem.readRowHitRate 80.91
222system.physmem.writeRowHitRate nan
223system.physmem.avgGap 39581.82
224system.physmem.pageHitRate 80.91
225system.physmem_0.actEnergy 564060
226system.physmem_0.preEnergy 273240
227system.physmem_0.readEnergy 2698920
228system.physmem_0.writeEnergy 0
229system.physmem_0.refreshEnergy 1229280.000000
230system.physmem_0.actBackEnergy 3964920
231system.physmem_0.preBackEnergy 25920
232system.physmem_0.actPowerDownEnergy 5979870
233system.physmem_0.prePowerDownEnergy 0
234system.physmem_0.selfRefreshEnergy 0
235system.physmem_0.totalEnergy 14736210
236system.physmem_0.averagePower 673.616822
237system.physmem_0.totalIdleTime 13059500
238system.physmem_0.memoryStateTime::IDLE 11500
239system.physmem_0.memoryStateTime::REF 520000
240system.physmem_0.memoryStateTime::SREF 0
241system.physmem_0.memoryStateTime::PRE_PDN 0
242system.physmem_0.memoryStateTime::ACT 8222000
243system.physmem_0.memoryStateTime::ACT_PDN 13122500
244system.physmem_1.actEnergy 185640
245system.physmem_1.preEnergy 83490
246system.physmem_1.readEnergy 1228080
247system.physmem_1.writeEnergy 0
248system.physmem_1.refreshEnergy 1229280.000000
249system.physmem_1.actBackEnergy 2123820
250system.physmem_1.preBackEnergy 198720
251system.physmem_1.actPowerDownEnergy 7360410
252system.physmem_1.prePowerDownEnergy 215040
253system.physmem_1.selfRefreshEnergy 0
254system.physmem_1.totalEnergy 12624480
255system.physmem_1.averagePower 577.086109
256system.physmem_1.totalIdleTime 16628250
257system.physmem_1.memoryStateTime::IDLE 448500
258system.physmem_1.memoryStateTime::REF 520000
259system.physmem_1.memoryStateTime::SREF 0
260system.physmem_1.memoryStateTime::PRE_PDN 559250
261system.physmem_1.memoryStateTime::ACT 4203750
262system.physmem_1.memoryStateTime::ACT_PDN 16144500
263system.pwrStateResidencyTicks::UNDEFINED 21876000
264system.cpu.branchPred.lookups 3602
265system.cpu.branchPred.condPredicted 2403
266system.cpu.branchPred.condIncorrect 615
267system.cpu.branchPred.BTBLookups 3064
268system.cpu.branchPred.BTBHits 820
269system.cpu.branchPred.BTBCorrect 0
270system.cpu.branchPred.BTBHitPct 26.762402
271system.cpu.branchPred.usedRAS 0
272system.cpu.branchPred.RASInCorrect 0
273system.cpu.branchPred.indirectLookups 552
274system.cpu.branchPred.indirectHits 26
275system.cpu.branchPred.indirectMisses 526
276system.cpu.branchPredindirectMispredicted 148
277system.cpu_clk_domain.clock 500
278system.cpu.dtb.read_hits 0
279system.cpu.dtb.read_misses 0
280system.cpu.dtb.read_accesses 0
281system.cpu.dtb.write_hits 0
282system.cpu.dtb.write_misses 0
283system.cpu.dtb.write_accesses 0
284system.cpu.dtb.hits 0
285system.cpu.dtb.misses 0
286system.cpu.dtb.accesses 0
287system.cpu.itb.read_hits 0
288system.cpu.itb.read_misses 0
289system.cpu.itb.read_accesses 0
290system.cpu.itb.write_hits 0
291system.cpu.itb.write_misses 0
292system.cpu.itb.write_accesses 0
293system.cpu.itb.hits 0
294system.cpu.itb.misses 0
295system.cpu.itb.accesses 0
296system.cpu.workload.numSyscalls 9
297system.cpu.pwrStateResidencyTicks::ON 21876000
298system.cpu.numCycles 43754
299system.cpu.numWorkItemsStarted 0
300system.cpu.numWorkItemsCompleted 0
301system.cpu.fetch.icacheStallCycles 9412
302system.cpu.fetch.Insts 15646
303system.cpu.fetch.Branches 3602
304system.cpu.fetch.predictedBranches 846
305system.cpu.fetch.Cycles 4159
306system.cpu.fetch.SquashCycles 1256
307system.cpu.fetch.MiscStallCycles 8
308system.cpu.fetch.IcacheWaitRetryStallCycles 99
309system.cpu.fetch.CacheLines 2183
310system.cpu.fetch.IcacheSquashes 446
311system.cpu.fetch.rateDist::samples 14306
312system.cpu.fetch.rateDist::mean 1.096323
313system.cpu.fetch.rateDist::stdev 2.511814
314system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
315system.cpu.fetch.rateDist::0 11573 80.90% 80.90%
316system.cpu.fetch.rateDist::1 217 1.52% 82.41%
317system.cpu.fetch.rateDist::2 240 1.68% 84.09%
318system.cpu.fetch.rateDist::3 172 1.20% 85.29%
319system.cpu.fetch.rateDist::4 322 2.25% 87.54%
320system.cpu.fetch.rateDist::5 235 1.64% 89.19%
321system.cpu.fetch.rateDist::6 104 0.73% 89.91%
322system.cpu.fetch.rateDist::7 160 1.12% 91.03%
323system.cpu.fetch.rateDist::8 1283 8.97% 100.00%
324system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
325system.cpu.fetch.rateDist::min_value 0
326system.cpu.fetch.rateDist::max_value 8
327system.cpu.fetch.rateDist::total 14306
328system.cpu.fetch.branchRate 0.082324
329system.cpu.fetch.rate 0.357590
330system.cpu.decode.IdleCycles 7306
331system.cpu.decode.BlockedCycles 4223
332system.cpu.decode.RunCycles 2169
333system.cpu.decode.UnblockCycles 153
334system.cpu.decode.SquashCycles 455
335system.cpu.decode.BranchResolved 898
336system.cpu.decode.BranchMispred 180
337system.cpu.decode.DecodedInsts 12831
338system.cpu.decode.SquashedInsts 509
339system.cpu.rename.SquashCycles 455
340system.cpu.rename.IdleCycles 7513
341system.cpu.rename.BlockCycles 808
342system.cpu.rename.serializeStallCycles 2339
343system.cpu.rename.RunCycles 2094
344system.cpu.rename.UnblockCycles 1097
345system.cpu.rename.RenamedInsts 11937
346system.cpu.rename.IQFullEvents 8
347system.cpu.rename.LQFullEvents 48
348system.cpu.rename.SQFullEvents 1030
349system.cpu.rename.RenamedOperands 8187
350system.cpu.rename.RenameLookups 15598
351system.cpu.rename.int_rename_lookups 15586
352system.cpu.rename.fp_rename_lookups 12
353system.cpu.rename.CommittedMaps 3562
354system.cpu.rename.UndoneMaps 4625
355system.cpu.rename.serializingInsts 43
356system.cpu.rename.tempSerializingInsts 46
357system.cpu.rename.skidInsts 628
358system.cpu.memDep0.insertedLoads 2300
359system.cpu.memDep0.insertedStores 1692
360system.cpu.memDep0.conflictingLoads 27
361system.cpu.memDep0.conflictingStores 6
362system.cpu.iq.iqInstsAdded 10454
363system.cpu.iq.iqNonSpecInstsAdded 57
364system.cpu.iq.iqInstsIssued 9212
365system.cpu.iq.iqSquashedInstsIssued 89
366system.cpu.iq.iqSquashedInstsExamined 4951
367system.cpu.iq.iqSquashedOperandsExamined 2778
368system.cpu.iq.iqSquashedNonSpecRemoved 30
369system.cpu.iq.issued_per_cycle::samples 14306
370system.cpu.iq.issued_per_cycle::mean 0.643926
371system.cpu.iq.issued_per_cycle::stdev 1.508549
372system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
373system.cpu.iq.issued_per_cycle::0 11171 78.09% 78.09%
374system.cpu.iq.issued_per_cycle::1 976 6.82% 84.91%
375system.cpu.iq.issued_per_cycle::2 626 4.38% 89.28%
376system.cpu.iq.issued_per_cycle::3 441 3.08% 92.37%
377system.cpu.iq.issued_per_cycle::4 429 3.00% 95.37%
378system.cpu.iq.issued_per_cycle::5 288 2.01% 97.38%
379system.cpu.iq.issued_per_cycle::6 199 1.39% 98.77%
380system.cpu.iq.issued_per_cycle::7 97 0.68% 99.45%
381system.cpu.iq.issued_per_cycle::8 79 0.55% 100.00%
382system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
383system.cpu.iq.issued_per_cycle::min_value 0
384system.cpu.iq.issued_per_cycle::max_value 8
385system.cpu.iq.issued_per_cycle::total 14306
386system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
387system.cpu.iq.fu_full::IntAlu 41 13.58% 13.58%
388system.cpu.iq.fu_full::IntMult 0 0.00% 13.58%
389system.cpu.iq.fu_full::IntDiv 0 0.00% 13.58%
390system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.58%
391system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.58%
392system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.58%
393system.cpu.iq.fu_full::FloatMult 0 0.00% 13.58%
394system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 13.58%
395system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.58%
396system.cpu.iq.fu_full::FloatMisc 0 0.00% 13.58%
397system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.58%
398system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.58%
399system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.58%
400system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.58%
401system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.58%
402system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.58%
403system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.58%
404system.cpu.iq.fu_full::SimdMult 0 0.00% 13.58%
405system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.58%
406system.cpu.iq.fu_full::SimdShift 0 0.00% 13.58%
407system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.58%
408system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.58%
409system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.58%
410system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.58%
411system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.58%
412system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.58%
413system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.58%
414system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.58%
415system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.58%
416system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.58%
417system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.58%
418system.cpu.iq.fu_full::MemRead 169 55.96% 69.54%
419system.cpu.iq.fu_full::MemWrite 89 29.47% 99.01%
420system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01%
421system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00%
422system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
423system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
424system.cpu.iq.FU_type_0::No_OpClass 10 0.11% 0.11%
425system.cpu.iq.FU_type_0::IntAlu 5557 60.32% 60.43%
426system.cpu.iq.FU_type_0::IntMult 4 0.04% 60.48%
427system.cpu.iq.FU_type_0::IntDiv 8 0.09% 60.56%
428system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.56%
429system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.56%
430system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.56%
431system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.56%
432system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.56%
433system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.56%
434system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.56%
435system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.56%
436system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.56%
437system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.56%
438system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.56%
439system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.56%
440system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.56%
441system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.56%
442system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.56%
443system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.56%
444system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.56%
445system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.56%
446system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.56%
447system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.56%
448system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.56%
449system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.56%
450system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.56%
451system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.56%
452system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.56%
453system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.56%
454system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.56%
455system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.56%
456system.cpu.iq.FU_type_0::MemRead 2130 23.12% 83.68%
457system.cpu.iq.FU_type_0::MemWrite 1491 16.19% 99.87%
458system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.87%
459system.cpu.iq.FU_type_0::FloatMemWrite 12 0.13% 100.00%
460system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
461system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
462system.cpu.iq.FU_type_0::total 9212
463system.cpu.iq.rate 0.210541
464system.cpu.iq.fu_busy_cnt 302
465system.cpu.iq.fu_busy_rate 0.032783
466system.cpu.iq.int_inst_queue_reads 33094
467system.cpu.iq.int_inst_queue_writes 15459
468system.cpu.iq.int_inst_queue_wakeup_accesses 8123
469system.cpu.iq.fp_inst_queue_reads 27
470system.cpu.iq.fp_inst_queue_writes 12
471system.cpu.iq.fp_inst_queue_wakeup_accesses 12
472system.cpu.iq.int_alu_accesses 9489
473system.cpu.iq.fp_alu_accesses 15
474system.cpu.iew.lsq.thread0.forwLoads 88
475system.cpu.iew.lsq.thread0.invAddrLoads 0
476system.cpu.iew.lsq.thread0.squashedLoads 1199
477system.cpu.iew.lsq.thread0.ignoredResponses 3
478system.cpu.iew.lsq.thread0.memOrderViolation 10
479system.cpu.iew.lsq.thread0.squashedStores 595
480system.cpu.iew.lsq.thread0.invAddrSwpfs 0
481system.cpu.iew.lsq.thread0.blockedLoads 0
482system.cpu.iew.lsq.thread0.rescheduledLoads 1
483system.cpu.iew.lsq.thread0.cacheBlocked 97
484system.cpu.iew.iewIdleCycles 0
485system.cpu.iew.iewSquashCycles 455
486system.cpu.iew.iewBlockCycles 618
487system.cpu.iew.iewUnblockCycles 202
488system.cpu.iew.iewDispatchedInsts 10510
489system.cpu.iew.iewDispSquashedInsts 196
490system.cpu.iew.iewDispLoadInsts 2300
491system.cpu.iew.iewDispStoreInsts 1692
492system.cpu.iew.iewDispNonSpecInsts 56
493system.cpu.iew.iewIQFullEvents 1
494system.cpu.iew.iewLSQFullEvents 203
495system.cpu.iew.memOrderViolationEvents 10
496system.cpu.iew.predictedTakenIncorrect 42
497system.cpu.iew.predictedNotTakenIncorrect 495
498system.cpu.iew.branchMispredicts 537
499system.cpu.iew.iewExecutedInsts 8674
500system.cpu.iew.iewExecLoadInsts 1961
501system.cpu.iew.iewExecSquashedInsts 538
502system.cpu.iew.exec_swp 0
503system.cpu.iew.exec_nop 0
504system.cpu.iew.exec_refs 3393
505system.cpu.iew.exec_branches 1884
506system.cpu.iew.exec_stores 1432
507system.cpu.iew.exec_rate 0.198245
508system.cpu.iew.wb_sent 8314
509system.cpu.iew.wb_count 8135
510system.cpu.iew.wb_producers 3137
511system.cpu.iew.wb_consumers 4620
512system.cpu.iew.wb_rate 0.185926
513system.cpu.iew.wb_fanout 0.679004
514system.cpu.commit.commitSquashedInsts 4964
515system.cpu.commit.commitNonSpecStalls 26
516system.cpu.commit.branchMispredicts 442
517system.cpu.commit.committed_per_cycle::samples 13342
518system.cpu.commit.committed_per_cycle::mean 0.416579
519system.cpu.commit.committed_per_cycle::stdev 1.298857
520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
521system.cpu.commit.committed_per_cycle::0 11360 85.14% 85.14%
522system.cpu.commit.committed_per_cycle::1 763 5.72% 90.86%
523system.cpu.commit.committed_per_cycle::2 416 3.12% 93.98%
524system.cpu.commit.committed_per_cycle::3 229 1.72% 95.70%
525system.cpu.commit.committed_per_cycle::4 224 1.68% 97.38%
526system.cpu.commit.committed_per_cycle::5 92 0.69% 98.07%
527system.cpu.commit.committed_per_cycle::6 49 0.37% 98.43%
528system.cpu.commit.committed_per_cycle::7 46 0.34% 98.78%
529system.cpu.commit.committed_per_cycle::8 163 1.22% 100.00%
530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
531system.cpu.commit.committed_per_cycle::min_value 0
532system.cpu.commit.committed_per_cycle::max_value 8
533system.cpu.commit.committed_per_cycle::total 13342
534system.cpu.commit.committedInsts 5550
535system.cpu.commit.committedOps 5558
536system.cpu.commit.swp_count 0
537system.cpu.commit.refs 2198
538system.cpu.commit.loads 1101
539system.cpu.commit.membars 1
540system.cpu.commit.branches 1205
541system.cpu.commit.fp_insts 12
542system.cpu.commit.int_insts 5557
543system.cpu.commit.function_calls 291
544system.cpu.commit.op_class_0::No_OpClass 1 0.02% 0.02%
545system.cpu.commit.op_class_0::IntAlu 3353 60.33% 60.35%
546system.cpu.commit.op_class_0::IntMult 2 0.04% 60.38%
547system.cpu.commit.op_class_0::IntDiv 4 0.07% 60.45%
548system.cpu.commit.op_class_0::FloatAdd 0 0.00% 60.45%
549system.cpu.commit.op_class_0::FloatCmp 0 0.00% 60.45%
550system.cpu.commit.op_class_0::FloatCvt 0 0.00% 60.45%
551system.cpu.commit.op_class_0::FloatMult 0 0.00% 60.45%
552system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.45%
553system.cpu.commit.op_class_0::FloatDiv 0 0.00% 60.45%
554system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.45%
555system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.45%
556system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.45%
557system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.45%
558system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.45%
559system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.45%
560system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.45%
561system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.45%
562system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.45%
563system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.45%
564system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.45%
565system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.45%
566system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.45%
567system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.45%
568system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.45%
569system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.45%
570system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.45%
571system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.45%
572system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.45%
573system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.45%
574system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.45%
575system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.45%
576system.cpu.commit.op_class_0::MemRead 1101 19.81% 80.26%
577system.cpu.commit.op_class_0::MemWrite 1085 19.52% 99.78%
578system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.78%
579system.cpu.commit.op_class_0::FloatMemWrite 12 0.22% 100.00%
580system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
581system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
582system.cpu.commit.op_class_0::total 5558
583system.cpu.commit.bw_lim_events 163
584system.cpu.rob.rob_reads 23597
585system.cpu.rob.rob_writes 22017
586system.cpu.timesIdled 220
587system.cpu.idleCycles 29448
588system.cpu.committedInsts 5550
589system.cpu.committedOps 5558
590system.cpu.cpi 7.883604
591system.cpu.cpi_total 7.883604
592system.cpu.ipc 0.126846
593system.cpu.ipc_total 0.126846
594system.cpu.int_regfile_reads 11245
595system.cpu.int_regfile_writes 5548
596system.cpu.fp_regfile_reads 12
597system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21876000
598system.cpu.dcache.tags.replacements 0
599system.cpu.dcache.tags.tagsinuse 93.567108
600system.cpu.dcache.tags.total_refs 2320
601system.cpu.dcache.tags.sampled_refs 154
602system.cpu.dcache.tags.avg_refs 15.064935
603system.cpu.dcache.tags.warmup_cycle 0
604system.cpu.dcache.tags.occ_blocks::cpu.data 93.567108
605system.cpu.dcache.tags.occ_percent::cpu.data 0.022844
606system.cpu.dcache.tags.occ_percent::total 0.022844
607system.cpu.dcache.tags.occ_task_id_blocks::1024 154
608system.cpu.dcache.tags.age_task_id_blocks_1024::0 45
609system.cpu.dcache.tags.age_task_id_blocks_1024::1 109
610system.cpu.dcache.tags.occ_task_id_percent::1024 0.037598
611system.cpu.dcache.tags.tag_accesses 5834
612system.cpu.dcache.tags.data_accesses 5834
613system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21876000
614system.cpu.dcache.ReadReq_hits::cpu.data 1574
615system.cpu.dcache.ReadReq_hits::total 1574
616system.cpu.dcache.WriteReq_hits::cpu.data 728
617system.cpu.dcache.WriteReq_hits::total 728
618system.cpu.dcache.LoadLockedReq_hits::cpu.data 10
619system.cpu.dcache.LoadLockedReq_hits::total 10
620system.cpu.dcache.StoreCondReq_hits::cpu.data 8
621system.cpu.dcache.StoreCondReq_hits::total 8
622system.cpu.dcache.demand_hits::cpu.data 2302
623system.cpu.dcache.demand_hits::total 2302
624system.cpu.dcache.overall_hits::cpu.data 2302
625system.cpu.dcache.overall_hits::total 2302
626system.cpu.dcache.ReadReq_misses::cpu.data 157
627system.cpu.dcache.ReadReq_misses::total 157
628system.cpu.dcache.WriteReq_misses::cpu.data 361
629system.cpu.dcache.WriteReq_misses::total 361
630system.cpu.dcache.LoadLockedReq_misses::cpu.data 2
631system.cpu.dcache.LoadLockedReq_misses::total 2
632system.cpu.dcache.demand_misses::cpu.data 518
633system.cpu.dcache.demand_misses::total 518
634system.cpu.dcache.overall_misses::cpu.data 518
635system.cpu.dcache.overall_misses::total 518
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971system.cpu.toL2Bus.trans_dist::ReadSharedReq 76
972system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 797
973system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309
974system.cpu.toL2Bus.pkt_count::total 1106
975system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25472
976system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9856
977system.cpu.toL2Bus.pkt_size::total 35328
978system.cpu.toL2Bus.snoops 0
979system.cpu.toL2Bus.snoopTraffic 0
980system.cpu.toL2Bus.snoop_fanout::samples 554
981system.cpu.toL2Bus.snoop_fanout::mean 0.003610
982system.cpu.toL2Bus.snoop_fanout::stdev 0.060030
983system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
984system.cpu.toL2Bus.snoop_fanout::0 552 99.64% 99.64%
985system.cpu.toL2Bus.snoop_fanout::1 2 0.36% 100.00%
986system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
987system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
988system.cpu.toL2Bus.snoop_fanout::min_value 0
989system.cpu.toL2Bus.snoop_fanout::max_value 1
990system.cpu.toL2Bus.snoop_fanout::total 554
991system.cpu.toL2Bus.reqLayer0.occupancy 277000
992system.cpu.toL2Bus.reqLayer0.utilization 1.3
993system.cpu.toL2Bus.respLayer0.occupancy 597000
994system.cpu.toL2Bus.respLayer0.utilization 2.7
995system.cpu.toL2Bus.respLayer1.occupancy 231000
996system.cpu.toL2Bus.respLayer1.utilization 1.1
997system.membus.snoop_filter.tot_requests 550
998system.membus.snoop_filter.hit_single_requests 0
999system.membus.snoop_filter.hit_multi_requests 0
1000system.membus.snoop_filter.tot_snoops 0
1001system.membus.snoop_filter.hit_single_snoops 0
1002system.membus.snoop_filter.hit_multi_snoops 0
1003system.membus.pwrStateResidencyTicks::UNDEFINED 21876000
1004system.membus.trans_dist::ReadResp 471
1005system.membus.trans_dist::ReadExReq 79
1006system.membus.trans_dist::ReadExResp 79
1007system.membus.trans_dist::ReadSharedReq 471
1008system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1100
1009system.membus.pkt_count::total 1100
1010system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 35200
1011system.membus.pkt_size::total 35200
1012system.membus.snoops 0
1013system.membus.snoopTraffic 0
1014system.membus.snoop_fanout::samples 550
1015system.membus.snoop_fanout::mean 0
1016system.membus.snoop_fanout::stdev 0
1017system.membus.snoop_fanout::underflows 0 0.00% 0.00%
1018system.membus.snoop_fanout::0 550 100.00% 100.00%
1019system.membus.snoop_fanout::1 0 0.00% 100.00%
1020system.membus.snoop_fanout::overflows 0 0.00% 100.00%
1021system.membus.snoop_fanout::min_value 0
1022system.membus.snoop_fanout::max_value 0
1023system.membus.snoop_fanout::total 550
1024system.membus.reqLayer0.occupancy 681000
1025system.membus.reqLayer0.utilization 3.1
1026system.membus.respLayer1.occupancy 2898500
1027system.membus.respLayer1.utilization 13.2
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