| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000008 # Number of seconds simulated 4sim_ticks 7939500 # Number of ticks simulated 5final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000008 # Number of seconds simulated 4sim_ticks 7939500 # Number of ticks simulated 5final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 22942 # Simulator instruction rate (inst/s) 8host_op_rate 22935 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 114711600 # Simulator tick rate (ticks/s) 10host_mem_usage 232976 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 81718 # Simulator instruction rate (inst/s) 8host_op_rate 81674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 408398393 # Simulator tick rate (ticks/s) 10host_mem_usage 251348 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 1587 # Number of instructions simulated 13sim_ops 1587 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory 19system.physmem.bytes_read::total 11648 # Number of bytes read from this memory --- 233 unchanged lines hidden (view full) --- 253system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank 254system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states 255system.physmem_1.memoryStateTime::REF 153250 # Time in different power states 256system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 257system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem_1.memoryStateTime::ACT 0 # Time in different power states 259system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states | 12sim_insts 1587 # Number of instructions simulated 13sim_ops 1587 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory 19system.physmem.bytes_read::total 11648 # Number of bytes read from this memory --- 233 unchanged lines hidden (view full) --- 253system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank 254system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states 255system.physmem_1.memoryStateTime::REF 153250 # Time in different power states 256system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 257system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem_1.memoryStateTime::ACT 0 # Time in different power states 259system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states |
| 261system.cpu.branchPred.lookups 1252 # Number of BP lookups 262system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted | 261system.cpu.branchPred.lookups 1255 # Number of BP lookups 262system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted |
| 263system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect | 263system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect |
| 264system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups 265system.cpu.branchPred.BTBHits 300 # Number of BTB hits | 264system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups 265system.cpu.branchPred.BTBHits 302 # Number of BTB hits |
| 266system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 266system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 267system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage | 267system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage |
| 268system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 269system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 268system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 269system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 270system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. 271system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 272system.cpu.branchPred.indirectMisses 228 # Number of indirect misses. | 270system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups. 271system.cpu.branchPred.indirectHits 24 # Number of indirect target hits. 272system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. |
| 273system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. 274system.cpu_clk_domain.clock 500 # Clock period in ticks 275system.cpu.dtb.read_hits 0 # DTB read hits 276system.cpu.dtb.read_misses 0 # DTB read misses 277system.cpu.dtb.read_accesses 0 # DTB read accesses 278system.cpu.dtb.write_hits 0 # DTB write hits 279system.cpu.dtb.write_misses 0 # DTB write misses 280system.cpu.dtb.write_accesses 0 # DTB write accesses --- 10 unchanged lines hidden (view full) --- 291system.cpu.itb.misses 0 # DTB misses 292system.cpu.itb.accesses 0 # DTB accesses 293system.cpu.workload.num_syscalls 9 # Number of system calls 294system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states 295system.cpu.numCycles 15880 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss | 273system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. 274system.cpu_clk_domain.clock 500 # Clock period in ticks 275system.cpu.dtb.read_hits 0 # DTB read hits 276system.cpu.dtb.read_misses 0 # DTB read misses 277system.cpu.dtb.read_accesses 0 # DTB read accesses 278system.cpu.dtb.write_hits 0 # DTB write hits 279system.cpu.dtb.write_misses 0 # DTB write misses 280system.cpu.dtb.write_accesses 0 # DTB write accesses --- 10 unchanged lines hidden (view full) --- 291system.cpu.itb.misses 0 # DTB misses 292system.cpu.itb.accesses 0 # DTB accesses 293system.cpu.workload.num_syscalls 9 # Number of system calls 294system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states 295system.cpu.numCycles 15880 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss |
| 299system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken | 299system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken |
| 302system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked 303system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing 304system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 305system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps 306system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR 307system.cpu.fetch.CacheLines 803 # Number of cache lines fetched 308system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed 309system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) | 302system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked 303system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing 304system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 305system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps 306system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR 307system.cpu.fetch.CacheLines 803 # Number of cache lines fetched 308system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed 309system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) |
| 310system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) | 310system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total) |
| 312system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) | 312system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) |
| 316system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total) |
| 321system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) | 321system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) |
| 326system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle 327system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle 328system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle 329system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked | 326system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle 327system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle 328system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle 329system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked |
| 330system.cpu.decode.RunCycles 756 # Number of cycles decode is running 331system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking 332system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing | 330system.cpu.decode.RunCycles 756 # Number of cycles decode is running 331system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking 332system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing |
| 333system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch | 333system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch |
| 334system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction | 334system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction |
| 335system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode | 335system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode |
| 336system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode 337system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing | 336system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode 337system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing |
| 338system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle 339system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking | 338system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle 339system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking |
| 340system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst | 340system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst |
| 341system.cpu.rename.RunCycles 672 # Number of cycles rename is running | 341system.cpu.rename.RunCycles 673 # Number of cycles rename is running |
| 342system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking | 342system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking |
| 343system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename | 343system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename |
| 344system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full | 344system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full |
| 345system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed 346system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made 347system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups | 345system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed 346system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made 347system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups |
| 348system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed | 348system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed |
| 349system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing | 349system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing |
| 350system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 351system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed 352system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer | 350system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 351system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed 352system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer |
| 353system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. 354system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. | 353system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit. 354system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. |
| 355system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. 356system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 355system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. 356system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 357system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) | 357system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec) |
| 358system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ | 358system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ |
| 359system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued | 359system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued |
| 360system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued | 360system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued |
| 361system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling 362system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph | 361system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling 362system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph |
| 363system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed 364system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle | 363system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed 364system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle |
| 365system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle | 365system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle |
| 367system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle | 367system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle |
| 370system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle |
| 375system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle 381system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 382system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available --- 29 unchanged lines hidden (view full) --- 412system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available 413system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 419system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued | 375system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle 381system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 382system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available --- 29 unchanged lines hidden (view full) --- 412system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available 413system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 419system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued |
| 420system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued 421system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued 422system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued | 420system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued 421system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued 422system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued |
| 453system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 453system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 457system.cpu.iq.FU_type_0::total 2694 # Type of FU issued 458system.cpu.iq.rate 0.169647 # Inst issue rate | 457system.cpu.iq.FU_type_0::total 2703 # Type of FU issued 458system.cpu.iq.rate 0.170214 # Inst issue rate |
| 459system.cpu.iq.fu_busy_cnt 70 # FU busy when requested | 459system.cpu.iq.fu_busy_cnt 70 # FU busy when requested |
| 460system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) 461system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads 462system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes 463system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses | 460system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst) 461system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads 462system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes 463system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses |
| 464system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 465system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 466system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 464system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 465system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 466system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 467system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses | 467system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses |
| 468system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 469system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores 470system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 468system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 469system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores 470system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 471system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed | 471system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed |
| 472system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 473system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations | 472system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 473system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations |
| 474system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed | 474system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed |
| 475system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 476system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 477system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 478system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 479system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 480system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing | 475system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 476system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 477system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 478system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 479system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 480system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing |
| 481system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking | 481system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking |
| 482system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking | 482system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking |
| 483system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ | 483system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ |
| 484system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch | 484system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch |
| 485system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions 486system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions | 485system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions 486system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions |
| 487system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions 488system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 489system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 490system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations 491system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly 492system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly 493system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute | 487system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions 488system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 489system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 490system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations 491system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly 492system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly 493system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute |
| 494system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions 495system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed 496system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute | 494system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions 495system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed 496system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute |
| 497system.cpu.iew.exec_swp 0 # number of swp insts executed 498system.cpu.iew.exec_nop 0 # number of nop insts executed | 497system.cpu.iew.exec_swp 0 # number of swp insts executed 498system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 499system.cpu.iew.exec_refs 847 # number of memory reference insts executed 500system.cpu.iew.exec_branches 563 # Number of branches executed | 499system.cpu.iew.exec_refs 846 # number of memory reference insts executed 500system.cpu.iew.exec_branches 566 # Number of branches executed |
| 501system.cpu.iew.exec_stores 375 # Number of stores executed | 501system.cpu.iew.exec_stores 375 # Number of stores executed |
| 502system.cpu.iew.exec_rate 0.154408 # Inst execution rate 503system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit 504system.cpu.iew.wb_count 2310 # cumulative count of insts written-back 505system.cpu.iew.wb_producers 793 # num instructions producing a value 506system.cpu.iew.wb_consumers 1130 # num instructions consuming a value 507system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle 508system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back 509system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit | 502system.cpu.iew.exec_rate 0.154849 # Inst execution rate 503system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit 504system.cpu.iew.wb_count 2318 # cumulative count of insts written-back 505system.cpu.iew.wb_producers 798 # num instructions producing a value 506system.cpu.iew.wb_consumers 1140 # num instructions consuming a value 507system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle 508system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back 509system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit |
| 510system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 511system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted | 510system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 511system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted |
| 512system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle | 512system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle |
| 515system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 515system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 516system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle | 516system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle |
| 522system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 528system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle | 528system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle |
| 529system.cpu.commit.committedInsts 1587 # Number of instructions committed 530system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed 531system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 532system.cpu.commit.refs 568 # Number of memory references committed 533system.cpu.commit.loads 289 # Number of loads committed 534system.cpu.commit.membars 0 # Number of memory barriers committed 535system.cpu.commit.branches 373 # Number of branches committed 536system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 571system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction 572system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction 573system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 574system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::total 1587 # Class of committed instruction 578system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached | 529system.cpu.commit.committedInsts 1587 # Number of instructions committed 530system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed 531system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 532system.cpu.commit.refs 568 # Number of memory references committed 533system.cpu.commit.loads 289 # Number of loads committed 534system.cpu.commit.membars 0 # Number of memory barriers committed 535system.cpu.commit.branches 373 # Number of branches committed 536system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 571system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction 572system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction 573system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 574system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::total 1587 # Class of committed instruction 578system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached |
| 579system.cpu.rob.rob_reads 7041 # The number of ROB reads 580system.cpu.rob.rob_writes 6340 # The number of ROB writes | 579system.cpu.rob.rob_reads 7050 # The number of ROB reads 580system.cpu.rob.rob_writes 6361 # The number of ROB writes |
| 581system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself 582system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling 583system.cpu.committedInsts 1587 # Number of Instructions Simulated 584system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated 585system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction 586system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads 587system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle 588system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads | 581system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself 582system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling 583system.cpu.committedInsts 1587 # Number of Instructions Simulated 584system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated 585system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction 586system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads 587system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle 588system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads |
| 589system.cpu.int_regfile_reads 3068 # number of integer regfile reads 590system.cpu.int_regfile_writes 1663 # number of integer regfile writes | 589system.cpu.int_regfile_reads 3116 # number of integer regfile reads 590system.cpu.int_regfile_writes 1668 # number of integer regfile writes |
| 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 0 # number of replacements 593system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use | 591system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.tags.replacements 0 # number of replacements 593system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use |
| 594system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. | 594system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks. |
| 595system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. | 595system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. |
| 596system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. | 596system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks. |
| 597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy 601system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 603system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id | 597system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor 599system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy 600system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy 601system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id 602system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 603system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id |
| 604system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses 605system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses | 604system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses 605system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses |
| 606system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states | 606system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states |
| 607system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits 608system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits | 607system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits 608system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits |
| 609system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits 610system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits | 609system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits 610system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits |
| 611system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits 612system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits 613system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits 614system.cpu.dcache.overall_hits::total 626 # number of overall hits | 611system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits 612system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits 613system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits 614system.cpu.dcache.overall_hits::total 625 # number of overall hits |
| 615system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses 616system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses 617system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 618system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 619system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses 620system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses 621system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses 622system.cpu.dcache.overall_misses::total 106 # number of overall misses 623system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles 624system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles 627system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles 628system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles 629system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles 630system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles | 615system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses 616system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses 617system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 618system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 619system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses 620system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses 621system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses 622system.cpu.dcache.overall_misses::total 106 # number of overall misses 623system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles 624system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles 627system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles 628system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles 629system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles 630system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles |
| 631system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) 632system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) | 631system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses) 632system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses) |
| 633system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) | 633system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) |
| 635system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses 636system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses 637system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses 638system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses 639system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses 640system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses | 635system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses 636system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses 637system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses 638system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses 639system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses 640system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses |
| 641system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses 642system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses | 641system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses 642system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses |
| 643system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses 644system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses 645system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses 646system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses | 643system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses 644system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses 645system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses 646system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses |
| 647system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency 648system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency 649system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency 650system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency 651system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 652system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency 653system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 654system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency --- 22 unchanged lines hidden (view full) --- 677system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles 681system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles 682system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles 683system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles 684system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles | 647system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency 648system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency 649system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency 650system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency 651system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 652system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency 653system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 654system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency --- 22 unchanged lines hidden (view full) --- 677system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles 681system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles 682system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles 683system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles 684system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles |
| 685system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses 686system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses | 685system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses 686system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses |
| 687system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses 688system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses | 687system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses 688system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses |
| 689system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses 690system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses 691system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses 692system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses | 689system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses 690system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses 691system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses 692system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses |
| 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency --- 300 unchanged lines hidden --- | 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency --- 300 unchanged lines hidden --- |