1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000008 # Number of seconds simulated 4sim_ticks 7939500 # Number of ticks simulated 5final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 81718 # Simulator instruction rate (inst/s) 8host_op_rate 81674 # Simulator op (including micro ops) rate (op/s) --- 276 unchanged lines hidden (view full) --- 285system.cpu.itb.read_misses 0 # DTB read misses 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_accesses 0 # DTB write accesses 290system.cpu.itb.hits 0 # DTB hits 291system.cpu.itb.misses 0 # DTB misses 292system.cpu.itb.accesses 0 # DTB accesses |
293system.cpu.workload.numSyscalls 9 # Number of system calls |
294system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states 295system.cpu.numCycles 15880 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss 299system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken --- 699 unchanged lines hidden --- |