7,11c7,11
< host_inst_rate 22942 # Simulator instruction rate (inst/s)
< host_op_rate 22935 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 114711600 # Simulator tick rate (ticks/s)
< host_mem_usage 232976 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 81718 # Simulator instruction rate (inst/s)
> host_op_rate 81674 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 408398393 # Simulator tick rate (ticks/s)
> host_mem_usage 251348 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
261,262c261,262
< system.cpu.branchPred.lookups 1252 # Number of BP lookups
< system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1255 # Number of BP lookups
> system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted
264,265c264,265
< system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 300 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 302 # Number of BTB hits
267c267
< system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage
270,272c270,272
< system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 228 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 24 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
299,301c299,301
< system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken
---
> system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken
310,311c310,311
< system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total)
316,320c316,320
< system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total)
326,329c326,329
< system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked
---
> system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked
333c333
< system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch
---
> system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch
335c335
< system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode
338,339c338,339
< system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking
---
> system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking
341c341
< system.cpu.rename.RunCycles 672 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 673 # Number of cycles rename is running
343c343
< system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename
345,347c345,347
< system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups
349c349
< system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing
353,354c353,354
< system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
357c357
< system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec)
359c359
< system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued
361,362c361,362
< system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph
365,366c365,366
< system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle
370,374c370,374
< system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle
420,452c420,452
< system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued
457,458c457,458
< system.cpu.iq.FU_type_0::total 2694 # Type of FU issued
< system.cpu.iq.rate 0.169647 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 2703 # Type of FU issued
> system.cpu.iq.rate 0.170214 # Inst issue rate
460,463c460,463
< system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses
467c467
< system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses
471c471
< system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed
474c474
< system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed
481c481
< system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking
483c483
< system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ
485,486c485,486
< system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
494,496c494,496
< system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute
499,500c499,500
< system.cpu.iew.exec_refs 847 # number of memory reference insts executed
< system.cpu.iew.exec_branches 563 # Number of branches executed
---
> system.cpu.iew.exec_refs 846 # number of memory reference insts executed
> system.cpu.iew.exec_branches 566 # Number of branches executed
502,509c502,509
< system.cpu.iew.exec_rate 0.154408 # Inst execution rate
< system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 2310 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 793 # num instructions producing a value
< system.cpu.iew.wb_consumers 1130 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_rate 0.154849 # Inst execution rate
> system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 2318 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 798 # num instructions producing a value
> system.cpu.iew.wb_consumers 1140 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit
512,514c512,514
< system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle
516,521c516,521
< system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle
528c528
< system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle
579,580c579,580
< system.cpu.rob.rob_reads 7041 # The number of ROB reads
< system.cpu.rob.rob_writes 6340 # The number of ROB writes
---
> system.cpu.rob.rob_reads 7050 # The number of ROB reads
> system.cpu.rob.rob_writes 6361 # The number of ROB writes
589,590c589,590
< system.cpu.int_regfile_reads 3068 # number of integer regfile reads
< system.cpu.int_regfile_writes 1663 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 3116 # number of integer regfile reads
> system.cpu.int_regfile_writes 1668 # number of integer regfile writes
594c594
< system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks.
596c596
< system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks.
604,605c604,605
< system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses
607,608c607,608
< system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits
611,614c611,614
< system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits
< system.cpu.dcache.overall_hits::total 626 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits
> system.cpu.dcache.overall_hits::total 625 # number of overall hits
631,632c631,632
< system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses)
635,640c635,640
< system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses
643,646c643,646
< system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses
685,686c685,686
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
689,692c689,692
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses
< host_inst_rate 22942 # Simulator instruction rate (inst/s)
< host_op_rate 22935 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 114711600 # Simulator tick rate (ticks/s)
< host_mem_usage 232976 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 81718 # Simulator instruction rate (inst/s)
> host_op_rate 81674 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 408398393 # Simulator tick rate (ticks/s)
> host_mem_usage 251348 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
261,262c261,262
< system.cpu.branchPred.lookups 1252 # Number of BP lookups
< system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1255 # Number of BP lookups
> system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted
264,265c264,265
< system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 300 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 302 # Number of BTB hits
267c267
< system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage
270,272c270,272
< system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 228 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 24 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
299,301c299,301
< system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken
---
> system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken
310,311c310,311
< system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total)
316,320c316,320
< system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total)
326,329c326,329
< system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked
---
> system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked
333c333
< system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch
---
> system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch
335c335
< system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode
338,339c338,339
< system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking
---
> system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking
341c341
< system.cpu.rename.RunCycles 672 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 673 # Number of cycles rename is running
343c343
< system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename
345,347c345,347
< system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups
349c349
< system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing
353,354c353,354
< system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
357c357
< system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec)
359c359
< system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued
361,362c361,362
< system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph
365,366c365,366
< system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle
370,374c370,374
< system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle
420,452c420,452
< system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued
457,458c457,458
< system.cpu.iq.FU_type_0::total 2694 # Type of FU issued
< system.cpu.iq.rate 0.169647 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 2703 # Type of FU issued
> system.cpu.iq.rate 0.170214 # Inst issue rate
460,463c460,463
< system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses
467c467
< system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses
471c471
< system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed
474c474
< system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed
481c481
< system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking
483c483
< system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ
485,486c485,486
< system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
494,496c494,496
< system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute
499,500c499,500
< system.cpu.iew.exec_refs 847 # number of memory reference insts executed
< system.cpu.iew.exec_branches 563 # Number of branches executed
---
> system.cpu.iew.exec_refs 846 # number of memory reference insts executed
> system.cpu.iew.exec_branches 566 # Number of branches executed
502,509c502,509
< system.cpu.iew.exec_rate 0.154408 # Inst execution rate
< system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 2310 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 793 # num instructions producing a value
< system.cpu.iew.wb_consumers 1130 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_rate 0.154849 # Inst execution rate
> system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 2318 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 798 # num instructions producing a value
> system.cpu.iew.wb_consumers 1140 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit
512,514c512,514
< system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle
516,521c516,521
< system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle
528c528
< system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle
579,580c579,580
< system.cpu.rob.rob_reads 7041 # The number of ROB reads
< system.cpu.rob.rob_writes 6340 # The number of ROB writes
---
> system.cpu.rob.rob_reads 7050 # The number of ROB reads
> system.cpu.rob.rob_writes 6361 # The number of ROB writes
589,590c589,590
< system.cpu.int_regfile_reads 3068 # number of integer regfile reads
< system.cpu.int_regfile_writes 1663 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 3116 # number of integer regfile reads
> system.cpu.int_regfile_writes 1668 # number of integer regfile writes
594c594
< system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks.
596c596
< system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks.
604,605c604,605
< system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses
607,608c607,608
< system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits
611,614c611,614
< system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits
< system.cpu.dcache.overall_hits::total 626 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits
> system.cpu.dcache.overall_hits::total 625 # number of overall hits
631,632c631,632
< system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses)
635,640c635,640
< system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses
643,646c643,646
< system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses
685,686c685,686
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
689,692c689,692
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses