1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {

--- 956 unchanged lines hidden (view full) ---

965 "sequential_access": false,
966 "assoc": 2
967 },
968 "path": "system.cpu",
969 "numRobs": 1,
970 "switched_out": false,
971 "smtLSQPolicy": "Partitioned",
972 "fetchBufferSize": 64,
973 "cacheStorePorts": 200,
974 "simpoint_start_insts": [],
975 "max_insts_any_thread": 0,
976 "smtROBThreshold": 100,
977 "numIQEntries": 64,
978 "branchPred": {
979 "numThreads": 1,
980 "BTBEntries": 4096,

--- 101 unchanged lines hidden (view full) ---

1082 "commitToRenameDelay": 1,
1083 "system": "system",
1084 "checker": null,
1085 "numPhysFloatRegs": 256,
1086 "eventq_index": 0,
1087 "default_p_state": "UNDEFINED",
1088 "type": "DerivO3CPU",
1089 "wbWidth": 8,
1090 "interrupts": [
1091 {
1092 "eventq_index": 0,
1093 "path": "system.cpu.interrupts",
1094 "type": "RiscvInterrupts",
1095 "name": "interrupts",
1096 "cxx_class": "RiscvISA::Interrupts"
1097 }

--- 56 unchanged lines hidden ---