Cross Reference: /gem5/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini

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config.ini (11731:c473ca7cc650)	config.ini (12062:d6ee16239a26)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred
68cachePorts=200	68cacheStorePorts=200
69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false	69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false
	142syscallRetryLatency=10000
142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180data_latency=2 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system 197tag_latency=2 198tags=system.cpu.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain 210data_latency=2 211default_p_state=UNDEFINED 212eventq_index=0 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=262144 219tag_latency=2 220 221[system.cpu.dtb] 222type=RiscvTLB 223eventq_index=0 224size=64 225 226[system.cpu.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 230eventq_index=0 231 232[system.cpu.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu.fuPool.FUList0.opList 238 239[system.cpu.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242opClass=IntAlu 243opLat=1 244pipelined=true 245 246[system.cpu.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 252 253[system.cpu.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256opClass=IntMult 257opLat=3 258pipelined=true 259 260[system.cpu.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263opClass=IntDiv 264opLat=20 265pipelined=false 266 267[system.cpu.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 273 274[system.cpu.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277opClass=FloatAdd 278opLat=2 279pipelined=true 280 281[system.cpu.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284opClass=FloatCmp 285opLat=2 286pipelined=true 287 288[system.cpu.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu.fuPool.FUList3] 296type=FUDesc 297children=opList0 opList1 opList2 opList3 opList4 298count=2 299eventq_index=0 300opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 301 302[system.cpu.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0 326opClass=FloatDiv 327opLat=12 328pipelined=false 329 330[system.cpu.fuPool.FUList3.opList4] 331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu.fuPool.FUList4] 338type=FUDesc 339children=opList0 opList1 340count=0 341eventq_index=0 342opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 343 344[system.cpu.fuPool.FUList4.opList0] 345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350 351[system.cpu.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357 358[system.cpu.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 364 365[system.cpu.fuPool.FUList5.opList00] 366type=OpDesc 367eventq_index=0 368opClass=SimdAdd 369opLat=1 370pipelined=true 371 372[system.cpu.fuPool.FUList5.opList01] 373type=OpDesc 374eventq_index=0 375opClass=SimdAddAcc 376opLat=1 377pipelined=true 378 379[system.cpu.fuPool.FUList5.opList02] 380type=OpDesc 381eventq_index=0 382opClass=SimdAlu 383opLat=1 384pipelined=true 385 386[system.cpu.fuPool.FUList5.opList03] 387type=OpDesc 388eventq_index=0 389opClass=SimdCmp 390opLat=1 391pipelined=true 392 393[system.cpu.fuPool.FUList5.opList04] 394type=OpDesc 395eventq_index=0 396opClass=SimdCvt 397opLat=1 398pipelined=true 399 400[system.cpu.fuPool.FUList5.opList05] 401type=OpDesc 402eventq_index=0 403opClass=SimdMisc 404opLat=1 405pipelined=true 406 407[system.cpu.fuPool.FUList5.opList06] 408type=OpDesc 409eventq_index=0 410opClass=SimdMult 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList5.opList07] 415type=OpDesc 416eventq_index=0 417opClass=SimdMultAcc 418opLat=1 419pipelined=true 420 421[system.cpu.fuPool.FUList5.opList08] 422type=OpDesc 423eventq_index=0 424opClass=SimdShift 425opLat=1 426pipelined=true 427 428[system.cpu.fuPool.FUList5.opList09] 429type=OpDesc 430eventq_index=0 431opClass=SimdShiftAcc 432opLat=1 433pipelined=true 434 435[system.cpu.fuPool.FUList5.opList10] 436type=OpDesc 437eventq_index=0 438opClass=SimdSqrt 439opLat=1 440pipelined=true 441 442[system.cpu.fuPool.FUList5.opList11] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatAdd 446opLat=1 447pipelined=true 448 449[system.cpu.fuPool.FUList5.opList12] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatAlu 453opLat=1 454pipelined=true 455 456[system.cpu.fuPool.FUList5.opList13] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatCmp 460opLat=1 461pipelined=true 462 463[system.cpu.fuPool.FUList5.opList14] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatCvt 467opLat=1 468pipelined=true 469 470[system.cpu.fuPool.FUList5.opList15] 471type=OpDesc 472eventq_index=0 473opClass=SimdFloatDiv 474opLat=1 475pipelined=true 476 477[system.cpu.fuPool.FUList5.opList16] 478type=OpDesc 479eventq_index=0 480opClass=SimdFloatMisc 481opLat=1 482pipelined=true 483 484[system.cpu.fuPool.FUList5.opList17] 485type=OpDesc 486eventq_index=0 487opClass=SimdFloatMult 488opLat=1 489pipelined=true 490 491[system.cpu.fuPool.FUList5.opList18] 492type=OpDesc 493eventq_index=0 494opClass=SimdFloatMultAcc 495opLat=1 496pipelined=true 497 498[system.cpu.fuPool.FUList5.opList19] 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList6] 506type=FUDesc 507children=opList0 opList1 508count=0 509eventq_index=0 510opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 511 512[system.cpu.fuPool.FUList6.opList0] 513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518 519[system.cpu.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525 526[system.cpu.fuPool.FUList7] 527type=FUDesc 528children=opList0 opList1 opList2 opList3 529count=4 530eventq_index=0 531opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 532 533[system.cpu.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546 547[system.cpu.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560 561[system.cpu.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu.fuPool.FUList8.opList 567 568[system.cpu.fuPool.FUList8.opList] 569type=OpDesc 570eventq_index=0 571opClass=IprAccess 572opLat=3 573pipelined=false 574 575[system.cpu.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=2 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl 582data_latency=2 583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0 586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=131072 598system=system 599tag_latency=2 600tags=system.cpu.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu.icache_port 605mem_side=system.cpu.toL2Bus.slave[0] 606 607[system.cpu.icache.tags] 608type=LRU 609assoc=2 610block_size=64 611clk_domain=system.cpu_clk_domain 612data_latency=2 613default_p_state=UNDEFINED 614eventq_index=0 615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=131072 621tag_latency=2 622 623[system.cpu.interrupts] 624type=RiscvInterrupts 625eventq_index=0 626 627[system.cpu.isa] 628type=RiscvISA 629eventq_index=0 630 631[system.cpu.itb] 632type=RiscvTLB 633eventq_index=0 634size=64 635 636[system.cpu.l2cache] 637type=Cache 638children=tags 639addr_ranges=0:18446744073709551615:0:0:0:0 640assoc=8 641clk_domain=system.cpu_clk_domain 642clusivity=mostly_incl 643data_latency=20 644default_p_state=UNDEFINED 645demand_mshr_reserve=1 646eventq_index=0 647is_read_only=false 648max_miss_count=0 649mshrs=20 650p_state_clk_gate_bins=20 651p_state_clk_gate_max=1000000000000 652p_state_clk_gate_min=1000 653power_model=Null 654prefetch_on_access=false 655prefetcher=Null 656response_latency=20 657sequential_access=false 658size=2097152 659system=system 660tag_latency=20 661tags=system.cpu.l2cache.tags 662tgts_per_mshr=12 663write_buffers=8 664writeback_clean=false 665cpu_side=system.cpu.toL2Bus.master[0] 666mem_side=system.membus.slave[1] 667 668[system.cpu.l2cache.tags] 669type=LRU 670assoc=8 671block_size=64 672clk_domain=system.cpu_clk_domain 673data_latency=20 674default_p_state=UNDEFINED 675eventq_index=0 676p_state_clk_gate_bins=20 677p_state_clk_gate_max=1000000000000 678p_state_clk_gate_min=1000 679power_model=Null 680sequential_access=false 681size=2097152 682tag_latency=20 683 684[system.cpu.toL2Bus] 685type=CoherentXBar 686children=snoop_filter 687clk_domain=system.cpu_clk_domain 688default_p_state=UNDEFINED 689eventq_index=0 690forward_latency=0 691frontend_latency=1 692p_state_clk_gate_bins=20 693p_state_clk_gate_max=1000000000000 694p_state_clk_gate_min=1000 695point_of_coherency=false 696power_model=Null 697response_latency=1 698snoop_filter=system.cpu.toL2Bus.snoop_filter 699snoop_response_latency=1 700system=system 701use_default_range=false 702width=32 703master=system.cpu.l2cache.cpu_side 704slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 705 706[system.cpu.toL2Bus.snoop_filter] 707type=SnoopFilter 708eventq_index=0 709lookup_latency=0 710max_capacity=8388608 711system=system 712 713[system.cpu.tracer] 714type=ExeTracer 715eventq_index=0 716 717[system.cpu.workload]	143system=system 144tracer=system.cpu.tracer 145trapLatency=13 146wbWidth=8 147workload=system.cpu.workload 148dcache_port=system.cpu.dcache.cpu_side 149icache_port=system.cpu.icache.cpu_side 150 151[system.cpu.branchPred] 152type=TournamentBP 153BTBEntries=4096 154BTBTagSize=16 155RASSize=16 156choiceCtrBits=2 157choicePredictorSize=8192 158eventq_index=0 159globalCtrBits=2 160globalPredictorSize=8192 161indirectHashGHR=true 162indirectHashTargets=true 163indirectPathLength=3 164indirectSets=256 165indirectTagSize=16 166indirectWays=2 167instShiftAmt=2 168localCtrBits=2 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181data_latency=2 182default_p_state=UNDEFINED 183demand_mshr_reserve=1 184eventq_index=0 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=262144 197system=system 198tag_latency=2 199tags=system.cpu.dcache.tags 200tgts_per_mshr=20 201write_buffers=8 202writeback_clean=false 203cpu_side=system.cpu.dcache_port 204mem_side=system.cpu.toL2Bus.slave[1] 205 206[system.cpu.dcache.tags] 207type=LRU 208assoc=2 209block_size=64 210clk_domain=system.cpu_clk_domain 211data_latency=2 212default_p_state=UNDEFINED 213eventq_index=0 214p_state_clk_gate_bins=20 215p_state_clk_gate_max=1000000000000 216p_state_clk_gate_min=1000 217power_model=Null 218sequential_access=false 219size=262144 220tag_latency=2 221 222[system.cpu.dtb] 223type=RiscvTLB 224eventq_index=0 225size=64 226 227[system.cpu.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 230FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 231eventq_index=0 232 233[system.cpu.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=6 237eventq_index=0 238opList=system.cpu.fuPool.FUList0.opList 239 240[system.cpu.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243opClass=IntAlu 244opLat=1 245pipelined=true 246 247[system.cpu.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 250count=2 251eventq_index=0 252opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 253 254[system.cpu.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257opClass=IntMult 258opLat=3 259pipelined=true 260 261[system.cpu.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264opClass=IntDiv 265opLat=20 266pipelined=false 267 268[system.cpu.fuPool.FUList2] 269type=FUDesc 270children=opList0 opList1 opList2 271count=4 272eventq_index=0 273opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 274 275[system.cpu.fuPool.FUList2.opList0] 276type=OpDesc 277eventq_index=0 278opClass=FloatAdd 279opLat=2 280pipelined=true 281 282[system.cpu.fuPool.FUList2.opList1] 283type=OpDesc 284eventq_index=0 285opClass=FloatCmp 286opLat=2 287pipelined=true 288 289[system.cpu.fuPool.FUList2.opList2] 290type=OpDesc 291eventq_index=0 292opClass=FloatCvt 293opLat=2 294pipelined=true 295 296[system.cpu.fuPool.FUList3] 297type=FUDesc 298children=opList0 opList1 opList2 opList3 opList4 299count=2 300eventq_index=0 301opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 302 303[system.cpu.fuPool.FUList3.opList0] 304type=OpDesc 305eventq_index=0 306opClass=FloatMult 307opLat=4 308pipelined=true 309 310[system.cpu.fuPool.FUList3.opList1] 311type=OpDesc 312eventq_index=0 313opClass=FloatMultAcc 314opLat=5 315pipelined=true 316 317[system.cpu.fuPool.FUList3.opList2] 318type=OpDesc 319eventq_index=0 320opClass=FloatMisc 321opLat=3 322pipelined=true 323 324[system.cpu.fuPool.FUList3.opList3] 325type=OpDesc 326eventq_index=0 327opClass=FloatDiv 328opLat=12 329pipelined=false 330 331[system.cpu.fuPool.FUList3.opList4] 332type=OpDesc 333eventq_index=0 334opClass=FloatSqrt 335opLat=24 336pipelined=false 337 338[system.cpu.fuPool.FUList4] 339type=FUDesc 340children=opList0 opList1 341count=0 342eventq_index=0 343opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 344 345[system.cpu.fuPool.FUList4.opList0] 346type=OpDesc 347eventq_index=0 348opClass=MemRead 349opLat=1 350pipelined=true 351 352[system.cpu.fuPool.FUList4.opList1] 353type=OpDesc 354eventq_index=0 355opClass=FloatMemRead 356opLat=1 357pipelined=true 358 359[system.cpu.fuPool.FUList5] 360type=FUDesc 361children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 362count=4 363eventq_index=0 364opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 365 366[system.cpu.fuPool.FUList5.opList00] 367type=OpDesc 368eventq_index=0 369opClass=SimdAdd 370opLat=1 371pipelined=true 372 373[system.cpu.fuPool.FUList5.opList01] 374type=OpDesc 375eventq_index=0 376opClass=SimdAddAcc 377opLat=1 378pipelined=true 379 380[system.cpu.fuPool.FUList5.opList02] 381type=OpDesc 382eventq_index=0 383opClass=SimdAlu 384opLat=1 385pipelined=true 386 387[system.cpu.fuPool.FUList5.opList03] 388type=OpDesc 389eventq_index=0 390opClass=SimdCmp 391opLat=1 392pipelined=true 393 394[system.cpu.fuPool.FUList5.opList04] 395type=OpDesc 396eventq_index=0 397opClass=SimdCvt 398opLat=1 399pipelined=true 400 401[system.cpu.fuPool.FUList5.opList05] 402type=OpDesc 403eventq_index=0 404opClass=SimdMisc 405opLat=1 406pipelined=true 407 408[system.cpu.fuPool.FUList5.opList06] 409type=OpDesc 410eventq_index=0 411opClass=SimdMult 412opLat=1 413pipelined=true 414 415[system.cpu.fuPool.FUList5.opList07] 416type=OpDesc 417eventq_index=0 418opClass=SimdMultAcc 419opLat=1 420pipelined=true 421 422[system.cpu.fuPool.FUList5.opList08] 423type=OpDesc 424eventq_index=0 425opClass=SimdShift 426opLat=1 427pipelined=true 428 429[system.cpu.fuPool.FUList5.opList09] 430type=OpDesc 431eventq_index=0 432opClass=SimdShiftAcc 433opLat=1 434pipelined=true 435 436[system.cpu.fuPool.FUList5.opList10] 437type=OpDesc 438eventq_index=0 439opClass=SimdSqrt 440opLat=1 441pipelined=true 442 443[system.cpu.fuPool.FUList5.opList11] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatAdd 447opLat=1 448pipelined=true 449 450[system.cpu.fuPool.FUList5.opList12] 451type=OpDesc 452eventq_index=0 453opClass=SimdFloatAlu 454opLat=1 455pipelined=true 456 457[system.cpu.fuPool.FUList5.opList13] 458type=OpDesc 459eventq_index=0 460opClass=SimdFloatCmp 461opLat=1 462pipelined=true 463 464[system.cpu.fuPool.FUList5.opList14] 465type=OpDesc 466eventq_index=0 467opClass=SimdFloatCvt 468opLat=1 469pipelined=true 470 471[system.cpu.fuPool.FUList5.opList15] 472type=OpDesc 473eventq_index=0 474opClass=SimdFloatDiv 475opLat=1 476pipelined=true 477 478[system.cpu.fuPool.FUList5.opList16] 479type=OpDesc 480eventq_index=0 481opClass=SimdFloatMisc 482opLat=1 483pipelined=true 484 485[system.cpu.fuPool.FUList5.opList17] 486type=OpDesc 487eventq_index=0 488opClass=SimdFloatMult 489opLat=1 490pipelined=true 491 492[system.cpu.fuPool.FUList5.opList18] 493type=OpDesc 494eventq_index=0 495opClass=SimdFloatMultAcc 496opLat=1 497pipelined=true 498 499[system.cpu.fuPool.FUList5.opList19] 500type=OpDesc 501eventq_index=0 502opClass=SimdFloatSqrt 503opLat=1 504pipelined=true 505 506[system.cpu.fuPool.FUList6] 507type=FUDesc 508children=opList0 opList1 509count=0 510eventq_index=0 511opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 512 513[system.cpu.fuPool.FUList6.opList0] 514type=OpDesc 515eventq_index=0 516opClass=MemWrite 517opLat=1 518pipelined=true 519 520[system.cpu.fuPool.FUList6.opList1] 521type=OpDesc 522eventq_index=0 523opClass=FloatMemWrite 524opLat=1 525pipelined=true 526 527[system.cpu.fuPool.FUList7] 528type=FUDesc 529children=opList0 opList1 opList2 opList3 530count=4 531eventq_index=0 532opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 533 534[system.cpu.fuPool.FUList7.opList0] 535type=OpDesc 536eventq_index=0 537opClass=MemRead 538opLat=1 539pipelined=true 540 541[system.cpu.fuPool.FUList7.opList1] 542type=OpDesc 543eventq_index=0 544opClass=MemWrite 545opLat=1 546pipelined=true 547 548[system.cpu.fuPool.FUList7.opList2] 549type=OpDesc 550eventq_index=0 551opClass=FloatMemRead 552opLat=1 553pipelined=true 554 555[system.cpu.fuPool.FUList7.opList3] 556type=OpDesc 557eventq_index=0 558opClass=FloatMemWrite 559opLat=1 560pipelined=true 561 562[system.cpu.fuPool.FUList8] 563type=FUDesc 564children=opList 565count=1 566eventq_index=0 567opList=system.cpu.fuPool.FUList8.opList 568 569[system.cpu.fuPool.FUList8.opList] 570type=OpDesc 571eventq_index=0 572opClass=IprAccess 573opLat=3 574pipelined=false 575 576[system.cpu.icache] 577type=Cache 578children=tags 579addr_ranges=0:18446744073709551615:0:0:0:0 580assoc=2 581clk_domain=system.cpu_clk_domain 582clusivity=mostly_incl 583data_latency=2 584default_p_state=UNDEFINED 585demand_mshr_reserve=1 586eventq_index=0 587is_read_only=true 588max_miss_count=0 589mshrs=4 590p_state_clk_gate_bins=20 591p_state_clk_gate_max=1000000000000 592p_state_clk_gate_min=1000 593power_model=Null 594prefetch_on_access=false 595prefetcher=Null 596response_latency=2 597sequential_access=false 598size=131072 599system=system 600tag_latency=2 601tags=system.cpu.icache.tags 602tgts_per_mshr=20 603write_buffers=8 604writeback_clean=true 605cpu_side=system.cpu.icache_port 606mem_side=system.cpu.toL2Bus.slave[0] 607 608[system.cpu.icache.tags] 609type=LRU 610assoc=2 611block_size=64 612clk_domain=system.cpu_clk_domain 613data_latency=2 614default_p_state=UNDEFINED 615eventq_index=0 616p_state_clk_gate_bins=20 617p_state_clk_gate_max=1000000000000 618p_state_clk_gate_min=1000 619power_model=Null 620sequential_access=false 621size=131072 622tag_latency=2 623 624[system.cpu.interrupts] 625type=RiscvInterrupts 626eventq_index=0 627 628[system.cpu.isa] 629type=RiscvISA 630eventq_index=0 631 632[system.cpu.itb] 633type=RiscvTLB 634eventq_index=0 635size=64 636 637[system.cpu.l2cache] 638type=Cache 639children=tags 640addr_ranges=0:18446744073709551615:0:0:0:0 641assoc=8 642clk_domain=system.cpu_clk_domain 643clusivity=mostly_incl 644data_latency=20 645default_p_state=UNDEFINED 646demand_mshr_reserve=1 647eventq_index=0 648is_read_only=false 649max_miss_count=0 650mshrs=20 651p_state_clk_gate_bins=20 652p_state_clk_gate_max=1000000000000 653p_state_clk_gate_min=1000 654power_model=Null 655prefetch_on_access=false 656prefetcher=Null 657response_latency=20 658sequential_access=false 659size=2097152 660system=system 661tag_latency=20 662tags=system.cpu.l2cache.tags 663tgts_per_mshr=12 664write_buffers=8 665writeback_clean=false 666cpu_side=system.cpu.toL2Bus.master[0] 667mem_side=system.membus.slave[1] 668 669[system.cpu.l2cache.tags] 670type=LRU 671assoc=8 672block_size=64 673clk_domain=system.cpu_clk_domain 674data_latency=20 675default_p_state=UNDEFINED 676eventq_index=0 677p_state_clk_gate_bins=20 678p_state_clk_gate_max=1000000000000 679p_state_clk_gate_min=1000 680power_model=Null 681sequential_access=false 682size=2097152 683tag_latency=20 684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 692frontend_latency=1 693p_state_clk_gate_bins=20 694p_state_clk_gate_max=1000000000000 695p_state_clk_gate_min=1000 696point_of_coherency=false 697power_model=Null 698response_latency=1 699snoop_filter=system.cpu.toL2Bus.snoop_filter 700snoop_response_latency=1 701system=system 702use_default_range=false 703width=32 704master=system.cpu.l2cache.cpu_side 705slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 706 707[system.cpu.toL2Bus.snoop_filter] 708type=SnoopFilter 709eventq_index=0 710lookup_latency=0 711max_capacity=8388608 712system=system 713 714[system.cpu.tracer] 715type=ExeTracer 716eventq_index=0 717 718[system.cpu.workload]
718type=LiveProcess	719type=Process
719cmd=hello 720cwd= 721drivers= 722egid=100 723env= 724errout=cerr 725euid=100 726eventq_index=0	720cmd=hello 721cwd= 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0
727executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello	728executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello
728gid=100 729input=cin 730kvmInSE=false	729gid=100 730input=cin 731kvmInSE=false
731max_stack_size=67108864	732maxStackSize=67108864
732output=cout	733output=cout
	734pgid=100
733pid=100	735pid=100
734ppid=99	736ppid=0
735simpoint=0 736system=system 737uid=100 738useArchPT=false 739 740[system.cpu_clk_domain] 741type=SrcClockDomain 742clock=500 743domain_id=-1 744eventq_index=0 745init_perf_level=0 746voltage_domain=system.voltage_domain 747 748[system.dvfs_handler] 749type=DVFSHandler 750domains= 751enable=false 752eventq_index=0 753sys_clk_domain=system.clk_domain 754transition_latency=100000000 755 756[system.membus] 757type=CoherentXBar 758children=snoop_filter 759clk_domain=system.clk_domain 760default_p_state=UNDEFINED 761eventq_index=0 762forward_latency=4 763frontend_latency=3 764p_state_clk_gate_bins=20 765p_state_clk_gate_max=1000000000000 766p_state_clk_gate_min=1000 767point_of_coherency=true 768power_model=Null 769response_latency=2 770snoop_filter=system.membus.snoop_filter 771snoop_response_latency=4 772system=system 773use_default_range=false 774width=16 775master=system.physmem.port 776slave=system.system_port system.cpu.l2cache.mem_side 777 778[system.membus.snoop_filter] 779type=SnoopFilter 780eventq_index=0 781lookup_latency=1 782max_capacity=8388608 783system=system 784 785[system.physmem] 786type=DRAMCtrl 787IDD0=0.055000 788IDD02=0.000000 789IDD2N=0.032000 790IDD2N2=0.000000 791IDD2P0=0.000000 792IDD2P02=0.000000 793IDD2P1=0.032000 794IDD2P12=0.000000 795IDD3N=0.038000 796IDD3N2=0.000000 797IDD3P0=0.000000 798IDD3P02=0.000000 799IDD3P1=0.038000 800IDD3P12=0.000000 801IDD4R=0.157000 802IDD4R2=0.000000 803IDD4W=0.125000 804IDD4W2=0.000000 805IDD5=0.235000 806IDD52=0.000000 807IDD6=0.020000 808IDD62=0.000000 809VDD=1.500000 810VDD2=0.000000 811activation_limit=4 812addr_mapping=RoRaBaCoCh 813bank_groups_per_rank=0 814banks_per_rank=8 815burst_length=8 816channels=1 817clk_domain=system.clk_domain 818conf_table_reported=true 819default_p_state=UNDEFINED 820device_bus_width=8 821device_rowbuffer_size=1024 822device_size=536870912 823devices_per_rank=8 824dll=true 825eventq_index=0 826in_addr_map=true 827kvm_map=true 828max_accesses_per_row=16 829mem_sched_policy=frfcfs 830min_writes_per_switch=16 831null=false 832p_state_clk_gate_bins=20 833p_state_clk_gate_max=1000000000000 834p_state_clk_gate_min=1000 835page_policy=open_adaptive 836power_model=Null 837range=0:134217727:0:0:0:0 838ranks_per_channel=2 839read_buffer_size=32 840static_backend_latency=10000 841static_frontend_latency=10000 842tBURST=5000 843tCCD_L=0 844tCK=1250 845tCL=13750 846tCS=2500 847tRAS=35000 848tRCD=13750 849tREFI=7800000 850tRFC=260000 851tRP=13750 852tRRD=6000 853tRRD_L=0 854tRTP=7500 855tRTW=2500 856tWR=15000 857tWTR=7500 858tXAW=30000 859tXP=6000 860tXPDLL=0 861tXS=270000 862tXSDLL=0 863write_buffer_size=64 864write_high_thresh_perc=85 865write_low_thresh_perc=50 866port=system.membus.master[0] 867 868[system.voltage_domain] 869type=VoltageDomain 870eventq_index=0 871voltage=1.000000 872	737simpoint=0 738system=system 739uid=100 740useArchPT=false 741 742[system.cpu_clk_domain] 743type=SrcClockDomain 744clock=500 745domain_id=-1 746eventq_index=0 747init_perf_level=0 748voltage_domain=system.voltage_domain 749 750[system.dvfs_handler] 751type=DVFSHandler 752domains= 753enable=false 754eventq_index=0 755sys_clk_domain=system.clk_domain 756transition_latency=100000000 757 758[system.membus] 759type=CoherentXBar 760children=snoop_filter 761clk_domain=system.clk_domain 762default_p_state=UNDEFINED 763eventq_index=0 764forward_latency=4 765frontend_latency=3 766p_state_clk_gate_bins=20 767p_state_clk_gate_max=1000000000000 768p_state_clk_gate_min=1000 769point_of_coherency=true 770power_model=Null 771response_latency=2 772snoop_filter=system.membus.snoop_filter 773snoop_response_latency=4 774system=system 775use_default_range=false 776width=16 777master=system.physmem.port 778slave=system.system_port system.cpu.l2cache.mem_side 779 780[system.membus.snoop_filter] 781type=SnoopFilter 782eventq_index=0 783lookup_latency=1 784max_capacity=8388608 785system=system 786 787[system.physmem] 788type=DRAMCtrl 789IDD0=0.055000 790IDD02=0.000000 791IDD2N=0.032000 792IDD2N2=0.000000 793IDD2P0=0.000000 794IDD2P02=0.000000 795IDD2P1=0.032000 796IDD2P12=0.000000 797IDD3N=0.038000 798IDD3N2=0.000000 799IDD3P0=0.000000 800IDD3P02=0.000000 801IDD3P1=0.038000 802IDD3P12=0.000000 803IDD4R=0.157000 804IDD4R2=0.000000 805IDD4W=0.125000 806IDD4W2=0.000000 807IDD5=0.235000 808IDD52=0.000000 809IDD6=0.020000 810IDD62=0.000000 811VDD=1.500000 812VDD2=0.000000 813activation_limit=4 814addr_mapping=RoRaBaCoCh 815bank_groups_per_rank=0 816banks_per_rank=8 817burst_length=8 818channels=1 819clk_domain=system.clk_domain 820conf_table_reported=true 821default_p_state=UNDEFINED 822device_bus_width=8 823device_rowbuffer_size=1024 824device_size=536870912 825devices_per_rank=8 826dll=true 827eventq_index=0 828in_addr_map=true 829kvm_map=true 830max_accesses_per_row=16 831mem_sched_policy=frfcfs 832min_writes_per_switch=16 833null=false 834p_state_clk_gate_bins=20 835p_state_clk_gate_max=1000000000000 836p_state_clk_gate_min=1000 837page_policy=open_adaptive 838power_model=Null 839range=0:134217727:0:0:0:0 840ranks_per_channel=2 841read_buffer_size=32 842static_backend_latency=10000 843static_frontend_latency=10000 844tBURST=5000 845tCCD_L=0 846tCK=1250 847tCL=13750 848tCS=2500 849tRAS=35000 850tRCD=13750 851tREFI=7800000 852tRFC=260000 853tRP=13750 854tRRD=6000 855tRRD_L=0 856tRTP=7500 857tRTW=2500 858tWR=15000 859tWTR=7500 860tXAW=30000 861tXP=6000 862tXPDLL=0 863tXS=270000 864tXSDLL=0 865write_buffer_size=64 866write_high_thresh_perc=85 867write_low_thresh_perc=50 868port=system.membus.master[0] 869 870[system.voltage_domain] 871type=VoltageDomain 872eventq_index=0 873voltage=1.000000 874