3sim_seconds 0.000014 # Number of seconds simulated
4sim_ticks 14435000 # Number of ticks simulated
5final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 136295 # Simulator instruction rate (inst/s)
8host_op_rate 136181 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1229999304 # Simulator tick rate (ticks/s)
10host_mem_usage 249560 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 1597 # Number of instructions simulated
13sim_ops 1597 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory
19system.physmem.bytes_read::total 12032 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 188 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 188 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 97 # Per bank write bursts
46system.physmem.perBankRdBursts::1 64 # Per bank write bursts
47system.physmem.perBankRdBursts::2 18 # Per bank write bursts
48system.physmem.perBankRdBursts::3 9 # Per bank write bursts
49system.physmem.perBankRdBursts::4 0 # Per bank write bursts
50system.physmem.perBankRdBursts::5 0 # Per bank write bursts
51system.physmem.perBankRdBursts::6 0 # Per bank write bursts
52system.physmem.perBankRdBursts::7 0 # Per bank write bursts
53system.physmem.perBankRdBursts::8 0 # Per bank write bursts
54system.physmem.perBankRdBursts::9 0 # Per bank write bursts
55system.physmem.perBankRdBursts::10 0 # Per bank write bursts
56system.physmem.perBankRdBursts::11 0 # Per bank write bursts
57system.physmem.perBankRdBursts::12 0 # Per bank write bursts
58system.physmem.perBankRdBursts::13 0 # Per bank write bursts
59system.physmem.perBankRdBursts::14 0 # Per bank write bursts
60system.physmem.perBankRdBursts::15 0 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 14206000 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 188 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation
200system.physmem.totQLat 1580250 # Total ticks spent queuing
201system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM
202system.physmem.totBusLat 940000 # Total ticks spent in databus transfers
203system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst
204system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
205system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst
206system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s
207system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
208system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s
209system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
210system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
211system.physmem.busUtil 6.51 # Data bus utilization in percentage
212system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads
213system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
214system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
215system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
216system.physmem.readRowHits 171 # Number of row buffer hits during reads
217system.physmem.writeRowHits 0 # Number of row buffer hits during writes
218system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads
219system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
220system.physmem.avgGap 75563.83 # Average gap between requests
221system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
222system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ)
223system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ)
224system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ)
225system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
226system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
227system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ)
228system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ)
229system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ)
230system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ)
231system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
232system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ)
233system.physmem_0.averagePower 603.160028 # Core power per rank (mW)
234system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank
235system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states
236system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
237system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
238system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states
239system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states
240system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states
241system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ)
242system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
243system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ)
244system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
245system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
246system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ)
247system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ)
248system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
249system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ)
250system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
251system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ)
252system.physmem_1.averagePower 427.808105 # Core power per rank (mW)
253system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
254system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states
255system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
256system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
257system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states
258system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
259system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
260system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
261system.cpu.branchPred.lookups 995 # Number of BP lookups
262system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted
263system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect
264system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups
265system.cpu.branchPred.BTBHits 100 # Number of BTB hits
266system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
267system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage
268system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
269system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
270system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups.
271system.cpu.branchPred.indirectHits 11 # Number of indirect target hits.
272system.cpu.branchPred.indirectMisses 191 # Number of indirect misses.
273system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
274system.cpu_clk_domain.clock 500 # Clock period in ticks
275system.cpu.dtb.read_hits 0 # DTB read hits
276system.cpu.dtb.read_misses 0 # DTB read misses
277system.cpu.dtb.read_accesses 0 # DTB read accesses
278system.cpu.dtb.write_hits 0 # DTB write hits
279system.cpu.dtb.write_misses 0 # DTB write misses
280system.cpu.dtb.write_accesses 0 # DTB write accesses
281system.cpu.dtb.hits 0 # DTB hits
282system.cpu.dtb.misses 0 # DTB misses
283system.cpu.dtb.accesses 0 # DTB accesses
284system.cpu.itb.read_hits 0 # DTB read hits
285system.cpu.itb.read_misses 0 # DTB read misses
286system.cpu.itb.read_accesses 0 # DTB read accesses
287system.cpu.itb.write_hits 0 # DTB write hits
288system.cpu.itb.write_misses 0 # DTB write misses
289system.cpu.itb.write_accesses 0 # DTB write accesses
290system.cpu.itb.hits 0 # DTB hits
291system.cpu.itb.misses 0 # DTB misses
292system.cpu.itb.accesses 0 # DTB accesses
293system.cpu.workload.numSyscalls 9 # Number of system calls
294system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states
295system.cpu.numCycles 28870 # number of cpu cycles simulated
296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
298system.cpu.committedInsts 1597 # Number of instructions committed
299system.cpu.committedOps 1597 # Number of ops (including micro ops) committed
300system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit
301system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
302system.cpu.cpi 18.077646 # CPI: cycles per instruction
303system.cpu.ipc 0.055317 # IPC: instructions per cycle
304system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction
305system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction
306system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction
307system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction
308system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction
309system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction
310system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction
311system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction
312system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction
313system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction
314system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction
315system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction
316system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction
317system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction
318system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction
319system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction
320system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction
321system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction
322system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction
323system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction
324system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction
325system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction
326system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction
327system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction
328system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction
329system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction
330system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction
331system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction
332system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction
333system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction
334system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction
335system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction
336system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction
337system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction
338system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
339system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
340system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
341system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
342system.cpu.op_class_0::total 1597 # Class of committed instruction
343system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked
344system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped
345system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
346system.cpu.dcache.tags.replacements 0 # number of replacements
347system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use
348system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks.
349system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
350system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks.
351system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
352system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor
353system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy
354system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy
355system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
356system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
357system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
358system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
359system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses
360system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses
361system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
362system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits
363system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits
364system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
365system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
366system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits
367system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits
368system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits
369system.cpu.dcache.overall_hits::total 645 # number of overall hits
370system.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses
371system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses
372system.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses
373system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses
374system.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses
375system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses
376system.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses
377system.cpu.dcache.overall_misses::total 44 # number of overall misses
378system.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles
379system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles
380system.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles
381system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles
382system.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles
383system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles
384system.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles
385system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles
386system.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses)
387system.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses)
388system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
389system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
390system.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses
391system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses
392system.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses
393system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses
394system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses
395system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses
396system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses
397system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses
398system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses
399system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses
400system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses
401system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses
402system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency
403system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency
404system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency
405system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency
406system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
407system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency
408system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
409system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency
410system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
411system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
412system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
413system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
414system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
415system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
416system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits
417system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits
418system.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
419system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
420system.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
421system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits
422system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses
423system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses
424system.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses
425system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses
426system.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses
427system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses
428system.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses
429system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses
430system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles
431system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles
432system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles
433system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles
434system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles
435system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles
436system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles
437system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles
438system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses
439system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses
440system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses
441system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses
442system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses
443system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses
444system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses
445system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses
446system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency
447system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency
448system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency
449system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency
450system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency
451system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
452system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency
453system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
454system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
455system.cpu.icache.tags.replacements 0 # number of replacements
456system.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use
457system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks.
458system.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks.
459system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks.
460system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
461system.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor
462system.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy
463system.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy
464system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id
465system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
466system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
467system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id
468system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses
469system.cpu.icache.tags.data_accesses 1889 # Number of data accesses
470system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
471system.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits
472system.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits
473system.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits
474system.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits
475system.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits
476system.cpu.icache.overall_hits::total 709 # number of overall hits
477system.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses
478system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses
479system.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses
480system.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses
481system.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses
482system.cpu.icache.overall_misses::total 157 # number of overall misses
483system.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles
484system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles
485system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles
486system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles
487system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles
488system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles
489system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses)
490system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses)
491system.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses
492system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses
493system.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) accesses
494system.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses
495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181293 # miss rate for ReadReq accesses
496system.cpu.icache.ReadReq_miss_rate::total 0.181293 # miss rate for ReadReq accesses
497system.cpu.icache.demand_miss_rate::cpu.inst 0.181293 # miss rate for demand accesses
498system.cpu.icache.demand_miss_rate::total 0.181293 # miss rate for demand accesses
499system.cpu.icache.overall_miss_rate::cpu.inst 0.181293 # miss rate for overall accesses
500system.cpu.icache.overall_miss_rate::total 0.181293 # miss rate for overall accesses
501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80003.184713 # average ReadReq miss latency
502system.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency
503system.cpu.icache.demand_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency
504system.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency
505system.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency
506system.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency
507system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
509system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
511system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
513system.cpu.icache.ReadReq_mshr_misses::cpu.inst 157 # number of ReadReq MSHR misses
514system.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
515system.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses
516system.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses
517system.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses
518system.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses
519system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12403500 # number of ReadReq MSHR miss cycles
520system.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles
521system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles
522system.cpu.icache.demand_mshr_miss_latency::total 12403500 # number of demand (read+write) MSHR miss cycles
523system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles
524system.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles
525system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses
526system.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses
527system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses
528system.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses
529system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses
530system.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses
531system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency
532system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency
533system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
534system.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
535system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
536system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
537system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
538system.cpu.l2cache.tags.replacements 0 # number of replacements
539system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use
540system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
541system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks.
542system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks.
543system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
544system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor
545system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor
546system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy
547system.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy
548system.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy
549system.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
550system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
551system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
552system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id
553system.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses
554system.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses
555system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
556system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
557system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
558system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
559system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
560system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
561system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
562system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
563system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
564system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
565system.cpu.l2cache.overall_hits::total 2 # number of overall hits
566system.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses
567system.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses
568system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses
569system.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses
570system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses
571system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses
572system.cpu.l2cache.demand_misses::cpu.inst 156 # number of demand (read+write) misses
573system.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses
574system.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses
575system.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses
576system.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses
577system.cpu.l2cache.overall_misses::total 188 # number of overall misses
578system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles
579system.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles
580system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles
581system.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles
582system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles
583system.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles
584system.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles
585system.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles
586system.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles
587system.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles
588system.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles
589system.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles
590system.cpu.l2cache.ReadExReq_accesses::cpu.data 17 # number of ReadExReq accesses(hits+misses)
591system.cpu.l2cache.ReadExReq_accesses::total 17 # number of ReadExReq accesses(hits+misses)
592system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses)
593system.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses)
594system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses)
595system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses)
596system.cpu.l2cache.demand_accesses::cpu.inst 157 # number of demand (read+write) accesses
597system.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses
598system.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses
599system.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses
600system.cpu.l2cache.overall_accesses::cpu.data 33 # number of overall (read+write) accesses
601system.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses
602system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
603system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
604system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993631 # miss rate for ReadCleanReq accesses
605system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses
606system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses
607system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses
608system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993631 # miss rate for demand accesses
609system.cpu.l2cache.demand_miss_rate::cpu.data 0.969697 # miss rate for demand accesses
610system.cpu.l2cache.demand_miss_rate::total 0.989474 # miss rate for demand accesses
611system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993631 # miss rate for overall accesses
612system.cpu.l2cache.overall_miss_rate::cpu.data 0.969697 # miss rate for overall accesses
613system.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses
614system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency
615system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency
616system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency
617system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency
618system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency
619system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency
620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency
622system.cpu.l2cache.demand_avg_miss_latency::total 78130.319149 # average overall miss latency
623system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
624system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency
625system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency
626system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
627system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
628system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
629system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
630system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
631system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
632system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses
633system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses
634system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses
635system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses
636system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses
637system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses
638system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses
639system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses
640system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
641system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses
642system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses
643system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses
644system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles
645system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles
646system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles
647system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles
648system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles
649system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles
650system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles
651system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles
652system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles
653system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles
654system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles
655system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles
656system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
657system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
658system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses
659system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses
660system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses
661system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses
662system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses
663system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses
664system.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses
665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses
666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses
667system.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses
668system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency
669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency
670system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency
671system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency
672system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency
673system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency
674system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
676system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
677system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
679system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
680system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter.
681system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
682system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
683system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
684system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
685system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
686system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
687system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution
688system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution
689system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution
690system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution
691system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution
692system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes)
693system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes)
694system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes)
695system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes)
696system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes)
697system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes)
698system.cpu.toL2Bus.snoops 0 # Total snoops (count)
699system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
700system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram
701system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram
702system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram
703system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
704system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram
705system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram
706system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
707system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
708system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
709system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
710system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram
711system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks)
712system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
713system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks)
714system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
715system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks)
716system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
717system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter.
718system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
719system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
720system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
721system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
722system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
723system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
724system.membus.trans_dist::ReadResp 171 # Transaction distribution
725system.membus.trans_dist::ReadExReq 17 # Transaction distribution
726system.membus.trans_dist::ReadExResp 17 # Transaction distribution
727system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution
728system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes)
729system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes)
730system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes)
731system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes)
732system.membus.snoops 0 # Total snoops (count)
733system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
734system.membus.snoop_fanout::samples 188 # Request fanout histogram
735system.membus.snoop_fanout::mean 0 # Request fanout histogram
736system.membus.snoop_fanout::stdev 0 # Request fanout histogram
737system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
738system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram
739system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
740system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
741system.membus.snoop_fanout::min_value 0 # Request fanout histogram
742system.membus.snoop_fanout::max_value 0 # Request fanout histogram
743system.membus.snoop_fanout::total 188 # Request fanout histogram
744system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks)
745system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
746system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks)
747system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
| 3sim_seconds 0.000042
4sim_ticks 41515000
5final_tick 41515000
6sim_freq 1000000000000
7host_inst_rate 25426
8host_op_rate 25461
9host_tick_rate 189862237
10host_mem_usage 277956
11host_seconds 0.22
12sim_insts 5559
13sim_ops 5567
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 41515000
17system.physmem.bytes_read::cpu.inst 25024
18system.physmem.bytes_read::cpu.data 9536
19system.physmem.bytes_read::total 34560
20system.physmem.bytes_inst_read::cpu.inst 25024
21system.physmem.bytes_inst_read::total 25024
22system.physmem.num_reads::cpu.inst 391
23system.physmem.num_reads::cpu.data 149
24system.physmem.num_reads::total 540
25system.physmem.bw_read::cpu.inst 602770083
26system.physmem.bw_read::cpu.data 229700108
27system.physmem.bw_read::total 832470191
28system.physmem.bw_inst_read::cpu.inst 602770083
29system.physmem.bw_inst_read::total 602770083
30system.physmem.bw_total::cpu.inst 602770083
31system.physmem.bw_total::cpu.data 229700108
32system.physmem.bw_total::total 832470191
33system.physmem.readReqs 540
34system.physmem.writeReqs 0
35system.physmem.readBursts 540
36system.physmem.writeBursts 0
37system.physmem.bytesReadDRAM 34560
38system.physmem.bytesReadWrQ 0
39system.physmem.bytesWritten 0
40system.physmem.bytesReadSys 34560
41system.physmem.bytesWrittenSys 0
42system.physmem.servicedByWrQ 0
43system.physmem.mergedWrBursts 0
44system.physmem.neitherReadNorWriteReqs 0
45system.physmem.perBankRdBursts::0 57
46system.physmem.perBankRdBursts::1 85
47system.physmem.perBankRdBursts::2 52
48system.physmem.perBankRdBursts::3 47
49system.physmem.perBankRdBursts::4 31
50system.physmem.perBankRdBursts::5 36
51system.physmem.perBankRdBursts::6 45
52system.physmem.perBankRdBursts::7 20
53system.physmem.perBankRdBursts::8 32
54system.physmem.perBankRdBursts::9 24
55system.physmem.perBankRdBursts::10 22
56system.physmem.perBankRdBursts::11 18
57system.physmem.perBankRdBursts::12 51
58system.physmem.perBankRdBursts::13 5
59system.physmem.perBankRdBursts::14 6
60system.physmem.perBankRdBursts::15 9
61system.physmem.perBankWrBursts::0 0
62system.physmem.perBankWrBursts::1 0
63system.physmem.perBankWrBursts::2 0
64system.physmem.perBankWrBursts::3 0
65system.physmem.perBankWrBursts::4 0
66system.physmem.perBankWrBursts::5 0
67system.physmem.perBankWrBursts::6 0
68system.physmem.perBankWrBursts::7 0
69system.physmem.perBankWrBursts::8 0
70system.physmem.perBankWrBursts::9 0
71system.physmem.perBankWrBursts::10 0
72system.physmem.perBankWrBursts::11 0
73system.physmem.perBankWrBursts::12 0
74system.physmem.perBankWrBursts::13 0
75system.physmem.perBankWrBursts::14 0
76system.physmem.perBankWrBursts::15 0
77system.physmem.numRdRetry 0
78system.physmem.numWrRetry 0
79system.physmem.totGap 41434000
80system.physmem.readPktSize::0 0
81system.physmem.readPktSize::1 0
82system.physmem.readPktSize::2 0
83system.physmem.readPktSize::3 0
84system.physmem.readPktSize::4 0
85system.physmem.readPktSize::5 0
86system.physmem.readPktSize::6 540
87system.physmem.writePktSize::0 0
88system.physmem.writePktSize::1 0
89system.physmem.writePktSize::2 0
90system.physmem.writePktSize::3 0
91system.physmem.writePktSize::4 0
92system.physmem.writePktSize::5 0
93system.physmem.writePktSize::6 0
94system.physmem.rdQLenPdf::0 454
95system.physmem.rdQLenPdf::1 77
96system.physmem.rdQLenPdf::2 9
97system.physmem.rdQLenPdf::3 0
98system.physmem.rdQLenPdf::4 0
99system.physmem.rdQLenPdf::5 0
100system.physmem.rdQLenPdf::6 0
101system.physmem.rdQLenPdf::7 0
102system.physmem.rdQLenPdf::8 0
103system.physmem.rdQLenPdf::9 0
104system.physmem.rdQLenPdf::10 0
105system.physmem.rdQLenPdf::11 0
106system.physmem.rdQLenPdf::12 0
107system.physmem.rdQLenPdf::13 0
108system.physmem.rdQLenPdf::14 0
109system.physmem.rdQLenPdf::15 0
110system.physmem.rdQLenPdf::16 0
111system.physmem.rdQLenPdf::17 0
112system.physmem.rdQLenPdf::18 0
113system.physmem.rdQLenPdf::19 0
114system.physmem.rdQLenPdf::20 0
115system.physmem.rdQLenPdf::21 0
116system.physmem.rdQLenPdf::22 0
117system.physmem.rdQLenPdf::23 0
118system.physmem.rdQLenPdf::24 0
119system.physmem.rdQLenPdf::25 0
120system.physmem.rdQLenPdf::26 0
121system.physmem.rdQLenPdf::27 0
122system.physmem.rdQLenPdf::28 0
123system.physmem.rdQLenPdf::29 0
124system.physmem.rdQLenPdf::30 0
125system.physmem.rdQLenPdf::31 0
126system.physmem.wrQLenPdf::0 0
127system.physmem.wrQLenPdf::1 0
128system.physmem.wrQLenPdf::2 0
129system.physmem.wrQLenPdf::3 0
130system.physmem.wrQLenPdf::4 0
131system.physmem.wrQLenPdf::5 0
132system.physmem.wrQLenPdf::6 0
133system.physmem.wrQLenPdf::7 0
134system.physmem.wrQLenPdf::8 0
135system.physmem.wrQLenPdf::9 0
136system.physmem.wrQLenPdf::10 0
137system.physmem.wrQLenPdf::11 0
138system.physmem.wrQLenPdf::12 0
139system.physmem.wrQLenPdf::13 0
140system.physmem.wrQLenPdf::14 0
141system.physmem.wrQLenPdf::15 0
142system.physmem.wrQLenPdf::16 0
143system.physmem.wrQLenPdf::17 0
144system.physmem.wrQLenPdf::18 0
145system.physmem.wrQLenPdf::19 0
146system.physmem.wrQLenPdf::20 0
147system.physmem.wrQLenPdf::21 0
148system.physmem.wrQLenPdf::22 0
149system.physmem.wrQLenPdf::23 0
150system.physmem.wrQLenPdf::24 0
151system.physmem.wrQLenPdf::25 0
152system.physmem.wrQLenPdf::26 0
153system.physmem.wrQLenPdf::27 0
154system.physmem.wrQLenPdf::28 0
155system.physmem.wrQLenPdf::29 0
156system.physmem.wrQLenPdf::30 0
157system.physmem.wrQLenPdf::31 0
158system.physmem.wrQLenPdf::32 0
159system.physmem.wrQLenPdf::33 0
160system.physmem.wrQLenPdf::34 0
161system.physmem.wrQLenPdf::35 0
162system.physmem.wrQLenPdf::36 0
163system.physmem.wrQLenPdf::37 0
164system.physmem.wrQLenPdf::38 0
165system.physmem.wrQLenPdf::39 0
166system.physmem.wrQLenPdf::40 0
167system.physmem.wrQLenPdf::41 0
168system.physmem.wrQLenPdf::42 0
169system.physmem.wrQLenPdf::43 0
170system.physmem.wrQLenPdf::44 0
171system.physmem.wrQLenPdf::45 0
172system.physmem.wrQLenPdf::46 0
173system.physmem.wrQLenPdf::47 0
174system.physmem.wrQLenPdf::48 0
175system.physmem.wrQLenPdf::49 0
176system.physmem.wrQLenPdf::50 0
177system.physmem.wrQLenPdf::51 0
178system.physmem.wrQLenPdf::52 0
179system.physmem.wrQLenPdf::53 0
180system.physmem.wrQLenPdf::54 0
181system.physmem.wrQLenPdf::55 0
182system.physmem.wrQLenPdf::56 0
183system.physmem.wrQLenPdf::57 0
184system.physmem.wrQLenPdf::58 0
185system.physmem.wrQLenPdf::59 0
186system.physmem.wrQLenPdf::60 0
187system.physmem.wrQLenPdf::61 0
188system.physmem.wrQLenPdf::62 0
189system.physmem.wrQLenPdf::63 0
190system.physmem.bytesPerActivate::samples 93
191system.physmem.bytesPerActivate::mean 353.720430
192system.physmem.bytesPerActivate::gmean 232.715538
193system.physmem.bytesPerActivate::stdev 313.050293
194system.physmem.bytesPerActivate::0-127 22 23.66% 23.66%
195system.physmem.bytesPerActivate::128-255 24 25.81% 49.46%
196system.physmem.bytesPerActivate::256-383 13 13.98% 63.44%
197system.physmem.bytesPerActivate::384-511 8 8.60% 72.04%
198system.physmem.bytesPerActivate::512-639 8 8.60% 80.65%
199system.physmem.bytesPerActivate::640-767 4 4.30% 84.95%
200system.physmem.bytesPerActivate::768-895 3 3.23% 88.17%
201system.physmem.bytesPerActivate::896-1023 2 2.15% 90.32%
202system.physmem.bytesPerActivate::1024-1151 9 9.68% 100.00%
203system.physmem.bytesPerActivate::total 93
204system.physmem.totQLat 6561250
205system.physmem.totMemAccLat 16686250
206system.physmem.totBusLat 2700000
207system.physmem.avgQLat 12150.46
208system.physmem.avgBusLat 5000.00
209system.physmem.avgMemAccLat 30900.46
210system.physmem.avgRdBW 832.47
211system.physmem.avgWrBW 0.00
212system.physmem.avgRdBWSys 832.47
213system.physmem.avgWrBWSys 0.00
214system.physmem.peakBW 12800.00
215system.physmem.busUtil 6.50
216system.physmem.busUtilRead 6.50
217system.physmem.busUtilWrite 0.00
218system.physmem.avgRdQLen 1.17
219system.physmem.avgWrQLen 0.00
220system.physmem.readRowHits 441
221system.physmem.writeRowHits 0
222system.physmem.readRowHitRate 81.67
223system.physmem.writeRowHitRate nan
224system.physmem.avgGap 76729.63
225system.physmem.pageHitRate 81.67
226system.physmem_0.actEnergy 506940
227system.physmem_0.preEnergy 254265
228system.physmem_0.readEnergy 2663220
229system.physmem_0.writeEnergy 0
230system.physmem_0.refreshEnergy 3073200.000000
231system.physmem_0.actBackEnergy 5192700
232system.physmem_0.preBackEnergy 69600
233system.physmem_0.actPowerDownEnergy 13337430
234system.physmem_0.prePowerDownEnergy 267840
235system.physmem_0.selfRefreshEnergy 0
236system.physmem_0.totalEnergy 25365195
237system.physmem_0.averagePower 610.988679
238system.physmem_0.totalIdleTime 29614500
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240system.physmem_0.memoryStateTime::REF 1300000
241system.physmem_0.memoryStateTime::SREF 0
242system.physmem_0.memoryStateTime::PRE_PDN 697500
243system.physmem_0.memoryStateTime::ACT 10229750
244system.physmem_0.memoryStateTime::ACT_PDN 29245750
245system.physmem_1.actEnergy 199920
246system.physmem_1.preEnergy 98670
247system.physmem_1.readEnergy 1192380
248system.physmem_1.writeEnergy 0
249system.physmem_1.refreshEnergy 3073200.000000
250system.physmem_1.actBackEnergy 2672160
251system.physmem_1.preBackEnergy 423840
252system.physmem_1.actPowerDownEnergy 14680350
253system.physmem_1.prePowerDownEnergy 905280
254system.physmem_1.selfRefreshEnergy 0
255system.physmem_1.totalEnergy 23245800
256system.physmem_1.averagePower 559.937372
257system.physmem_1.totalIdleTime 34511250
258system.physmem_1.memoryStateTime::IDLE 951000
259system.physmem_1.memoryStateTime::REF 1300000
260system.physmem_1.memoryStateTime::SREF 0
261system.physmem_1.memoryStateTime::PRE_PDN 2357000
262system.physmem_1.memoryStateTime::ACT 4708500
263system.physmem_1.memoryStateTime::ACT_PDN 32198500
264system.pwrStateResidencyTicks::UNDEFINED 41515000
265system.cpu.branchPred.lookups 2636
266system.cpu.branchPred.condPredicted 1784
267system.cpu.branchPred.condIncorrect 465
268system.cpu.branchPred.BTBLookups 2341
269system.cpu.branchPred.BTBHits 368
270system.cpu.branchPred.BTBCorrect 0
271system.cpu.branchPred.BTBHitPct 15.719778
272system.cpu.branchPred.usedRAS 0
273system.cpu.branchPred.RASInCorrect 0
274system.cpu.branchPred.indirectLookups 365
275system.cpu.branchPred.indirectHits 21
276system.cpu.branchPred.indirectMisses 344
277system.cpu.branchPredindirectMispredicted 123
278system.cpu_clk_domain.clock 500
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280system.cpu.dtb.read_misses 0
281system.cpu.dtb.read_accesses 0
282system.cpu.dtb.write_hits 0
283system.cpu.dtb.write_misses 0
284system.cpu.dtb.write_accesses 0
285system.cpu.dtb.hits 0
286system.cpu.dtb.misses 0
287system.cpu.dtb.accesses 0
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290system.cpu.itb.read_accesses 0
291system.cpu.itb.write_hits 0
292system.cpu.itb.write_misses 0
293system.cpu.itb.write_accesses 0
294system.cpu.itb.hits 0
295system.cpu.itb.misses 0
296system.cpu.itb.accesses 0
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301system.cpu.numWorkItemsCompleted 0
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303system.cpu.committedOps 5567
304system.cpu.discardedOps 1408
305system.cpu.numFetchSuspends 0
306system.cpu.cpi 14.936140
307system.cpu.ipc 0.066952
308system.cpu.op_class_0::No_OpClass 10 0.18% 0.18%
309system.cpu.op_class_0::IntAlu 3353 60.23% 60.41%
310system.cpu.op_class_0::IntMult 2 0.04% 60.45%
311system.cpu.op_class_0::IntDiv 4 0.07% 60.52%
312system.cpu.op_class_0::FloatAdd 0 0.00% 60.52%
313system.cpu.op_class_0::FloatCmp 0 0.00% 60.52%
314system.cpu.op_class_0::FloatCvt 0 0.00% 60.52%
315system.cpu.op_class_0::FloatMult 0 0.00% 60.52%
316system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.52%
317system.cpu.op_class_0::FloatDiv 0 0.00% 60.52%
318system.cpu.op_class_0::FloatMisc 0 0.00% 60.52%
319system.cpu.op_class_0::FloatSqrt 0 0.00% 60.52%
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322system.cpu.op_class_0::SimdAlu 0 0.00% 60.52%
323system.cpu.op_class_0::SimdCmp 0 0.00% 60.52%
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325system.cpu.op_class_0::SimdMisc 0 0.00% 60.52%
326system.cpu.op_class_0::SimdMult 0 0.00% 60.52%
327system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.52%
328system.cpu.op_class_0::SimdShift 0 0.00% 60.52%
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330system.cpu.op_class_0::SimdSqrt 0 0.00% 60.52%
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332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.52%
333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.52%
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336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.52%
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338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.52%
339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.52%
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341system.cpu.op_class_0::MemWrite 1085 19.49% 99.78%
342system.cpu.op_class_0::FloatMemRead 0 0.00% 99.78%
343system.cpu.op_class_0::FloatMemWrite 12 0.22% 100.00%
344system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
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364system.cpu.dcache.tags.data_accesses 4927
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