1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {
--- 1072 unchanged lines hidden (view full) ---
1081 ],
1082 "errout": "cerr",
1083 "useArchPT": false,
1084 "egid": 100,
1085 "output": "cout"
1086 }
1087 ],
1088 "name": "cpu",
1089 "dtb": {
1090 "name": "dtb",
1091 "eventq_index": 0,
1092 "cxx_class": "RiscvISA::TLB",
1093 "path": "system.cpu.dtb",
1094 "type": "RiscvTLB",
1095 "size": 64
1096 },
--- 117 unchanged lines hidden ---
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {
--- 1072 unchanged lines hidden (view full) ---
1081 ],
1082 "errout": "cerr",
1083 "useArchPT": false,
1084 "egid": 100,
1085 "output": "cout"
1086 }
1087 ],
1088 "name": "cpu",
1089 "dtb": {
1090 "name": "dtb",
1091 "eventq_index": 0,
1092 "cxx_class": "RiscvISA::TLB",
1093 "path": "system.cpu.dtb",
1094 "type": "RiscvTLB",
1095 "size": 64
1096 },
--- 117 unchanged lines hidden ---