| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 81 unchanged lines hidden (view full) --- 90output=cout 91pid=100 92ppid=99 93simpoint=0 94system=system 95uid=100 96 97[system.membus] |
| 98type=CoherentBus |
| 99block_size=64 |
| 100clock=1000 101header_cycles=1 102use_default_range=false 103width=64 104master=system.physmem.port[0] 105slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 106 107[system.physmem] 108type=SimpleMemory 109conf_table_reported=false 110file= 111in_addr_map=true 112latency=30000 113latency_var=0 114null=false 115range=0:134217727 116zero=false 117port=system.membus.master[0] 118 |