Cross Reference: /gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000010 # Number of seconds simulated
4sim_ticks 10184500 # Number of ticks simulated
5final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000014 # Number of seconds simulated
4sim_ticks 14081500 # Number of ticks simulated
5final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 98086 # Simulator instruction rate (inst/s)
8host_op_rate 98064 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 172399568 # Simulator tick rate (ticks/s)
10host_mem_usage 213936 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host

7host_inst_rate 87308 # Simulator instruction rate (inst/s)
8host_op_rate 87279 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 212126284 # Simulator tick rate (ticks/s)
10host_mem_usage 214180 # Number of bytes of host memory used
11host_seconds 0.07 # Real time elapsed on the host

12sim_insts 5792 # Number of instructions simulated
13sim_ops 5792 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory

14system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory

16system.physmem.bytes_read::total 29056 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory

16system.physmem.bytes_read::total 28992 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory

20system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory

21system.physmem.num_reads::total 454 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 454 # Total number of read requests seen

21system.physmem.num_reads::total 453 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 453 # Total number of read requests seen

31system.physmem.writeReqs 0 # Total number of write requests seen

32system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 29056 # Total number of bytes read from memory

32system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 28992 # Total number of bytes read from memory

34system.physmem.bytesWritten 0 # Total number of bytes written to memory

35system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize()

35system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize()

36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis

45system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis

45system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis

46system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis

--- 11 unchanged lines hidden (view full) ---

65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 10067000 # Total gap between requests

73system.physmem.totGap 13946000 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes

80system.physmem.readPktSize::6 454 # Categorize read packet sizes

80system.physmem.readPktSize::6 453 # Categorize read packet sizes

81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes

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93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

101system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see

106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 45 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

167system.physmem.totQLat 2091454 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests
169system.physmem.totBusLat 1816000 # Total cycles spent in databus access
170system.physmem.totBankLat 7406000 # Total cycles spent in bank access
171system.physmem.avgQLat 4606.73 # Average queueing delay per request
172system.physmem.avgBankLat 16312.78 # Average bank access latency per request

167system.physmem.totQLat 1940453 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests
169system.physmem.totBusLat 1812000 # Total cycles spent in databus access
170system.physmem.totBankLat 7462000 # Total cycles spent in bank access
171system.physmem.avgQLat 4283.56 # Average queueing delay per request
172system.physmem.avgBankLat 16472.41 # Average bank access latency per request

173system.physmem.avgBusLat 4000.00 # Average bus latency per request

174system.physmem.avgMemAccLat 24919.50 # Average memory access latency
175system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s

174system.physmem.avgMemAccLat 24755.97 # Average memory access latency
175system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s

176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s

177system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s

177system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s

178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s

180system.physmem.busUtil 17.83 # Data bus utilization in percentage
181system.physmem.avgRdQLen 1.11 # Average read queue length over time

180system.physmem.busUtil 12.87 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.80 # Average read queue length over time

182system.physmem.avgWrQLen 0.00 # Average write queue length over time

183system.physmem.readRowHits 377 # Number of row buffer hits during reads

183system.physmem.readRowHits 376 # Number of row buffer hits during reads

184system.physmem.writeRowHits 0 # Number of row buffer hits during writes

185system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads

185system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads

186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 22174.01 # Average gap between requests

187system.physmem.avgGap 30785.87 # Average gap between requests

188system.cpu.dtb.read_hits 0 # DTB read hits
189system.cpu.dtb.read_misses 0 # DTB read misses
190system.cpu.dtb.read_accesses 0 # DTB read accesses
191system.cpu.dtb.write_hits 0 # DTB write hits
192system.cpu.dtb.write_misses 0 # DTB write misses
193system.cpu.dtb.write_accesses 0 # DTB write accesses
194system.cpu.dtb.hits 0 # DTB hits
195system.cpu.dtb.misses 0 # DTB misses
196system.cpu.dtb.accesses 0 # DTB accesses
197system.cpu.itb.read_hits 0 # DTB read hits
198system.cpu.itb.read_misses 0 # DTB read misses
199system.cpu.itb.read_accesses 0 # DTB read accesses
200system.cpu.itb.write_hits 0 # DTB write hits
201system.cpu.itb.write_misses 0 # DTB write misses
202system.cpu.itb.write_accesses 0 # DTB write accesses
203system.cpu.itb.hits 0 # DTB hits
204system.cpu.itb.misses 0 # DTB misses
205system.cpu.itb.accesses 0 # DTB accesses
206system.cpu.workload.num_syscalls 9 # Number of system calls

207system.cpu.numCycles 20370 # number of cpu cycles simulated

207system.cpu.numCycles 28164 # number of cpu cycles simulated

208system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
209system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

210system.cpu.BPredUnit.lookups 2504 # Number of BP lookups
211system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted
212system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect
213system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups

210system.cpu.BPredUnit.lookups 2468 # Number of BP lookups
211system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted
212system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
213system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups

214system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits
215system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

216system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.

216system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target.

217system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.

218system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss
219system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed
220system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered
221system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken
222system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked
223system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing
224system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked
225system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
226system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched
227system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed
228system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total)
229system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total)
230system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total)

218system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss
219system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
220system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered
221system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken
222system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked
223system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing
224system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked
225system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
226system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
227system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched
228system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed
229system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total)
230system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total)
231system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total)

231system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

232system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

232system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total)
233system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total)

233system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total)

241system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
242system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

242system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

244system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle
246system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle
247system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle
248system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked
249system.cpu.decode.RunCycles 2237 # Number of cycles decode is running
250system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking
251system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing
252system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch
253system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
254system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode
255system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode
256system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing
257system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle
258system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking
259system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst
260system.cpu.rename.RunCycles 2090 # Number of cycles rename is running
261system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking
262system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename
263system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
264system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full
265system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed
266system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made
267system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups

245system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle
247system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle
248system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle
249system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked
250system.cpu.decode.RunCycles 2216 # Number of cycles decode is running
251system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
252system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing
253system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch
254system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
255system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode
256system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
257system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing
258system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle
259system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking
260system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst
261system.cpu.rename.RunCycles 2079 # Number of cycles rename is running
262system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking
263system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename
264system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
265system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full
266system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed
267system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made
268system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups

268system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
269system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed

269system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
270system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed

270system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing
271system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
272system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
273system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer

271system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing
272system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
273system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
274system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer

274system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit.

275system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit.

275system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit.

276system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit.

276system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.

277system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.

277system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores.
278system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec)

278system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores.
279system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec)

279system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ

280system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ

280system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued
281system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued
282system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling
283system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph

281system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued
282system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued
283system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling
284system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph

284system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed

285system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed

285system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle
286system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle
287system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle

286system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle
287system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle
288system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle

288system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

289system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

289system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle
290system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle
296system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle
297system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle

290system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle
296system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle
297system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle
298system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle

298system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
299system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

299system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

301system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle

302system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle

302system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

303system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

303system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available
304system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available
305system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available
306system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available
307system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available
308system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
312system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available
313system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available
314system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
332system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available
333system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available

304system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available
305system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available
306system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available
307system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available
308system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available
312system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
313system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available
314system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
333system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available
334system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available

334system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
335system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
336system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

335system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
336system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
337system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

337system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued
338system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
339system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
340system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued
341system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued
342system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued
346system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued
347system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued
348system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued
366system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued
367system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued

338system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued
339system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued
340system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued
341system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued
342system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued
346system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued
347system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued
348system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued
367system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued
368system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued

368system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
369system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

369system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
370system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

370system.cpu.iq.FU_type_0::total 9314 # Type of FU issued
371system.cpu.iq.rate 0.457241 # Inst issue rate
372system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
373system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst)
374system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads
375system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes
376system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses

371system.cpu.iq.FU_type_0::total 9281 # Type of FU issued
372system.cpu.iq.rate 0.329534 # Inst issue rate
373system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
374system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst)
375system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads
376system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes
377system.cpu.iq.int_inst_queue_wakeup_accesses 8398 # Number of integer instruction queue wakeup accesses

377system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
378system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
379system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses

378system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
379system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
380system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses

380system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses

381system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses

381system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses

382system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses

382system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores

383system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores

383system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
384system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed
385system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
386system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations

384system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
385system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed
386system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
387system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations

387system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed

388system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed

388system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
389system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
390system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled

389system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
390system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
391system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled

391system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked

392system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked

392system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

393system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

393system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
394system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
395system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
396system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ
397system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch

394system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing
395system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking
396system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
397system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ
398system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch

398system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions

399system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions

399system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions

400system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions

400system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions

401system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions

401system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
402system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall

402system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
403system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall

403system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations

404system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations

404system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly
405system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
406system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
407system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions
408system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed
409system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute

405system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly
406system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
407system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute
408system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions
409system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed
410system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute

410system.cpu.iew.exec_swp 0 # number of swp insts executed
411system.cpu.iew.exec_nop 0 # number of nop insts executed

411system.cpu.iew.exec_swp 0 # number of swp insts executed
412system.cpu.iew.exec_nop 0 # number of nop insts executed

412system.cpu.iew.exec_refs 3293 # number of memory reference insts executed
413system.cpu.iew.exec_branches 1392 # Number of branches executed

413system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
414system.cpu.iew.exec_branches 1388 # Number of branches executed

414system.cpu.iew.exec_stores 1577 # Number of stores executed

415system.cpu.iew.exec_stores 1577 # Number of stores executed

415system.cpu.iew.exec_rate 0.432351 # Inst execution rate
416system.cpu.iew.wb_sent 8605 # cumulative count of insts sent to commit
417system.cpu.iew.wb_count 8444 # cumulative count of insts written-back
418system.cpu.iew.wb_producers 4397 # num instructions producing a value
419system.cpu.iew.wb_consumers 7138 # num instructions consuming a value

416system.cpu.iew.exec_rate 0.312314 # Inst execution rate
417system.cpu.iew.wb_sent 8586 # cumulative count of insts sent to commit
418system.cpu.iew.wb_count 8425 # cumulative count of insts written-back
419system.cpu.iew.wb_producers 4372 # num instructions producing a value
420system.cpu.iew.wb_consumers 7073 # num instructions consuming a value

420system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

421system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

421system.cpu.iew.wb_rate 0.414531 # insts written-back per cycle
422system.cpu.iew.wb_fanout 0.615999 # average fanout of values written-back

422system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle
423system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back

423system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

424system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

424system.cpu.commit.commitSquashedInsts 5240 # The number of squashed insts skipped by commit

425system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit

425system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
426system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted

426system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
427system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted

427system.cpu.commit.committed_per_cycle::samples 10544 # Number of insts commited each cycle
428system.cpu.commit.committed_per_cycle::mean 0.549317 # Number of insts commited each cycle
429system.cpu.commit.committed_per_cycle::stdev 1.355880 # Number of insts commited each cycle

428system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle
429system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle
430system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle

430system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

431system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

431system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle
432system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::2 623 5.91% 92.85% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::3 255 2.42% 95.27% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::7 41 0.39% 98.99% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::8 107 1.01% 100.00% # Number of insts commited each cycle

432system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle
440system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle

440system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
441system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

441system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

443system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle

444system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle

444system.cpu.commit.committedInsts 5792 # Number of instructions committed
445system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
446system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
447system.cpu.commit.refs 2007 # Number of memory references committed
448system.cpu.commit.loads 961 # Number of loads committed
449system.cpu.commit.membars 7 # Number of memory barriers committed
450system.cpu.commit.branches 1037 # Number of branches committed
451system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
452system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
453system.cpu.commit.function_calls 103 # Number of function calls committed.

445system.cpu.commit.committedInsts 5792 # Number of instructions committed
446system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
447system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
448system.cpu.commit.refs 2007 # Number of memory references committed
449system.cpu.commit.loads 961 # Number of loads committed
450system.cpu.commit.membars 7 # Number of memory barriers committed
451system.cpu.commit.branches 1037 # Number of branches committed
452system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
453system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
454system.cpu.commit.function_calls 103 # Number of function calls committed.

454system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached

455system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached

455system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

456system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

456system.cpu.rob.rob_reads 21469 # The number of ROB reads
457system.cpu.rob.rob_writes 22869 # The number of ROB writes
458system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself
459system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling

457system.cpu.rob.rob_reads 21870 # The number of ROB reads
458system.cpu.rob.rob_writes 22837 # The number of ROB writes
459system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
460system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling

460system.cpu.committedInsts 5792 # Number of Instructions Simulated
461system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
462system.cpu.committedInsts_total 5792 # Number of Instructions Simulated

461system.cpu.committedInsts 5792 # Number of Instructions Simulated
462system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
463system.cpu.committedInsts_total 5792 # Number of Instructions Simulated

463system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction
464system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads
465system.cpu.ipc 0.284340 # IPC: Instructions Per Cycle
466system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads
467system.cpu.int_regfile_reads 13990 # number of integer regfile reads
468system.cpu.int_regfile_writes 7309 # number of integer regfile writes

464system.cpu.cpi 4.862569 # CPI: Cycles Per Instruction
465system.cpu.cpi_total 4.862569 # CPI: Total CPI of All Threads
466system.cpu.ipc 0.205653 # IPC: Instructions Per Cycle
467system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads
468system.cpu.int_regfile_reads 13961 # number of integer regfile reads
469system.cpu.int_regfile_writes 7286 # number of integer regfile writes

469system.cpu.fp_regfile_reads 25 # number of floating regfile reads
470system.cpu.fp_regfile_writes 2 # number of floating regfile writes
471system.cpu.icache.replacements 0 # number of replacements

470system.cpu.fp_regfile_reads 25 # number of floating regfile reads
471system.cpu.fp_regfile_writes 2 # number of floating regfile writes
472system.cpu.icache.replacements 0 # number of replacements

472system.cpu.icache.tagsinuse 172.348292 # Cycle average of tags in use
473system.cpu.icache.total_refs 1461 # Total number of references to valid blocks.
474system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks.
475system.cpu.icache.avg_refs 4.092437 # Average number of references to valid blocks.

473system.cpu.icache.tagsinuse 171.601938 # Cycle average of tags in use
474system.cpu.icache.total_refs 1437 # Total number of references to valid blocks.
475system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks.
476system.cpu.icache.avg_refs 4.036517 # Average number of references to valid blocks.

476system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

477system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

477system.cpu.icache.occ_blocks::cpu.inst 172.348292 # Average occupied blocks per requestor
478system.cpu.icache.occ_percent::cpu.inst 0.084154 # Average percentage of cache occupancy
479system.cpu.icache.occ_percent::total 0.084154 # Average percentage of cache occupancy
480system.cpu.icache.ReadReq_hits::cpu.inst 1461 # number of ReadReq hits
481system.cpu.icache.ReadReq_hits::total 1461 # number of ReadReq hits
482system.cpu.icache.demand_hits::cpu.inst 1461 # number of demand (read+write) hits
483system.cpu.icache.demand_hits::total 1461 # number of demand (read+write) hits
484system.cpu.icache.overall_hits::cpu.inst 1461 # number of overall hits
485system.cpu.icache.overall_hits::total 1461 # number of overall hits
486system.cpu.icache.ReadReq_misses::cpu.inst 426 # number of ReadReq misses
487system.cpu.icache.ReadReq_misses::total 426 # number of ReadReq misses
488system.cpu.icache.demand_misses::cpu.inst 426 # number of demand (read+write) misses
489system.cpu.icache.demand_misses::total 426 # number of demand (read+write) misses
490system.cpu.icache.overall_misses::cpu.inst 426 # number of overall misses
491system.cpu.icache.overall_misses::total 426 # number of overall misses
492system.cpu.icache.ReadReq_miss_latency::cpu.inst 13125000 # number of ReadReq miss cycles
493system.cpu.icache.ReadReq_miss_latency::total 13125000 # number of ReadReq miss cycles
494system.cpu.icache.demand_miss_latency::cpu.inst 13125000 # number of demand (read+write) miss cycles
495system.cpu.icache.demand_miss_latency::total 13125000 # number of demand (read+write) miss cycles
496system.cpu.icache.overall_miss_latency::cpu.inst 13125000 # number of overall miss cycles
497system.cpu.icache.overall_miss_latency::total 13125000 # number of overall miss cycles
498system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses)
499system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses)
500system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses
501system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses
502system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses
503system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses
504system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225755 # miss rate for ReadReq accesses
505system.cpu.icache.ReadReq_miss_rate::total 0.225755 # miss rate for ReadReq accesses
506system.cpu.icache.demand_miss_rate::cpu.inst 0.225755 # miss rate for demand accesses
507system.cpu.icache.demand_miss_rate::total 0.225755 # miss rate for demand accesses
508system.cpu.icache.overall_miss_rate::cpu.inst 0.225755 # miss rate for overall accesses
509system.cpu.icache.overall_miss_rate::total 0.225755 # miss rate for overall accesses
510system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30809.859155 # average ReadReq miss latency
511system.cpu.icache.ReadReq_avg_miss_latency::total 30809.859155 # average ReadReq miss latency
512system.cpu.icache.demand_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency
513system.cpu.icache.demand_avg_miss_latency::total 30809.859155 # average overall miss latency
514system.cpu.icache.overall_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency
515system.cpu.icache.overall_avg_miss_latency::total 30809.859155 # average overall miss latency
516system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

478system.cpu.icache.occ_blocks::cpu.inst 171.601938 # Average occupied blocks per requestor
479system.cpu.icache.occ_percent::cpu.inst 0.083790 # Average percentage of cache occupancy
480system.cpu.icache.occ_percent::total 0.083790 # Average percentage of cache occupancy
481system.cpu.icache.ReadReq_hits::cpu.inst 1437 # number of ReadReq hits
482system.cpu.icache.ReadReq_hits::total 1437 # number of ReadReq hits
483system.cpu.icache.demand_hits::cpu.inst 1437 # number of demand (read+write) hits
484system.cpu.icache.demand_hits::total 1437 # number of demand (read+write) hits
485system.cpu.icache.overall_hits::cpu.inst 1437 # number of overall hits
486system.cpu.icache.overall_hits::total 1437 # number of overall hits
487system.cpu.icache.ReadReq_misses::cpu.inst 440 # number of ReadReq misses
488system.cpu.icache.ReadReq_misses::total 440 # number of ReadReq misses
489system.cpu.icache.demand_misses::cpu.inst 440 # number of demand (read+write) misses
490system.cpu.icache.demand_misses::total 440 # number of demand (read+write) misses
491system.cpu.icache.overall_misses::cpu.inst 440 # number of overall misses
492system.cpu.icache.overall_misses::total 440 # number of overall misses
493system.cpu.icache.ReadReq_miss_latency::cpu.inst 20404500 # number of ReadReq miss cycles
494system.cpu.icache.ReadReq_miss_latency::total 20404500 # number of ReadReq miss cycles
495system.cpu.icache.demand_miss_latency::cpu.inst 20404500 # number of demand (read+write) miss cycles
496system.cpu.icache.demand_miss_latency::total 20404500 # number of demand (read+write) miss cycles
497system.cpu.icache.overall_miss_latency::cpu.inst 20404500 # number of overall miss cycles
498system.cpu.icache.overall_miss_latency::total 20404500 # number of overall miss cycles
499system.cpu.icache.ReadReq_accesses::cpu.inst 1877 # number of ReadReq accesses(hits+misses)
500system.cpu.icache.ReadReq_accesses::total 1877 # number of ReadReq accesses(hits+misses)
501system.cpu.icache.demand_accesses::cpu.inst 1877 # number of demand (read+write) accesses
502system.cpu.icache.demand_accesses::total 1877 # number of demand (read+write) accesses
503system.cpu.icache.overall_accesses::cpu.inst 1877 # number of overall (read+write) accesses
504system.cpu.icache.overall_accesses::total 1877 # number of overall (read+write) accesses
505system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234417 # miss rate for ReadReq accesses
506system.cpu.icache.ReadReq_miss_rate::total 0.234417 # miss rate for ReadReq accesses
507system.cpu.icache.demand_miss_rate::cpu.inst 0.234417 # miss rate for demand accesses
508system.cpu.icache.demand_miss_rate::total 0.234417 # miss rate for demand accesses
509system.cpu.icache.overall_miss_rate::cpu.inst 0.234417 # miss rate for overall accesses
510system.cpu.icache.overall_miss_rate::total 0.234417 # miss rate for overall accesses
511system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46373.863636 # average ReadReq miss latency
512system.cpu.icache.ReadReq_avg_miss_latency::total 46373.863636 # average ReadReq miss latency
513system.cpu.icache.demand_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency
514system.cpu.icache.demand_avg_miss_latency::total 46373.863636 # average overall miss latency
515system.cpu.icache.overall_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency
516system.cpu.icache.overall_avg_miss_latency::total 46373.863636 # average overall miss latency
517system.cpu.icache.blocked_cycles::no_mshrs 338 # number of cycles access was blocked

517system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

518system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

518system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked

519system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked

519system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

520system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

520system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

521system.cpu.icache.avg_blocked_cycles::no_mshrs 56.333333 # average number of cycles each access was blocked

521system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
522system.cpu.icache.fast_writes 0 # number of fast writes performed
523system.cpu.icache.cache_copies 0 # number of cache copies performed

522system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
523system.cpu.icache.fast_writes 0 # number of fast writes performed
524system.cpu.icache.cache_copies 0 # number of cache copies performed

524system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
525system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
526system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
527system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
528system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
529system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
530system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses
531system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses
532system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses
533system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses
534system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses
535system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses
536system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10853500 # number of ReadReq MSHR miss cycles
537system.cpu.icache.ReadReq_mshr_miss_latency::total 10853500 # number of ReadReq MSHR miss cycles
538system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10853500 # number of demand (read+write) MSHR miss cycles
539system.cpu.icache.demand_mshr_miss_latency::total 10853500 # number of demand (read+write) MSHR miss cycles
540system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10853500 # number of overall MSHR miss cycles
541system.cpu.icache.overall_mshr_miss_latency::total 10853500 # number of overall MSHR miss cycles
542system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for ReadReq accesses
543system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189189 # mshr miss rate for ReadReq accesses
544system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for demand accesses
545system.cpu.icache.demand_mshr_miss_rate::total 0.189189 # mshr miss rate for demand accesses
546system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for overall accesses
547system.cpu.icache.overall_mshr_miss_rate::total 0.189189 # mshr miss rate for overall accesses
548system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30401.960784 # average ReadReq mshr miss latency
549system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30401.960784 # average ReadReq mshr miss latency
550system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency
551system.cpu.icache.demand_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency
552system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency
553system.cpu.icache.overall_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency

525system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84 # number of ReadReq MSHR hits
526system.cpu.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
527system.cpu.icache.demand_mshr_hits::cpu.inst 84 # number of demand (read+write) MSHR hits
528system.cpu.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
529system.cpu.icache.overall_mshr_hits::cpu.inst 84 # number of overall MSHR hits
530system.cpu.icache.overall_mshr_hits::total 84 # number of overall MSHR hits
531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses
532system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
533system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses
534system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
535system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses
536system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses
537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17051500 # number of ReadReq MSHR miss cycles
538system.cpu.icache.ReadReq_mshr_miss_latency::total 17051500 # number of ReadReq MSHR miss cycles
539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17051500 # number of demand (read+write) MSHR miss cycles
540system.cpu.icache.demand_mshr_miss_latency::total 17051500 # number of demand (read+write) MSHR miss cycles
541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17051500 # number of overall MSHR miss cycles
542system.cpu.icache.overall_mshr_miss_latency::total 17051500 # number of overall MSHR miss cycles
543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for ReadReq accesses
544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189664 # mshr miss rate for ReadReq accesses
545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for demand accesses
546system.cpu.icache.demand_mshr_miss_rate::total 0.189664 # mshr miss rate for demand accesses
547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for overall accesses
548system.cpu.icache.overall_mshr_miss_rate::total 0.189664 # mshr miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47897.471910 # average ReadReq mshr miss latency
550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47897.471910 # average ReadReq mshr miss latency
551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency
552system.cpu.icache.demand_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency
553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency
554system.cpu.icache.overall_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency

554system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
555system.cpu.dcache.replacements 0 # number of replacements

555system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
556system.cpu.dcache.replacements 0 # number of replacements

556system.cpu.dcache.tagsinuse 63.058180 # Cycle average of tags in use
557system.cpu.dcache.total_refs 2201 # Total number of references to valid blocks.

557system.cpu.dcache.tagsinuse 63.108123 # Cycle average of tags in use
558system.cpu.dcache.total_refs 2206 # Total number of references to valid blocks.

558system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.

559system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.

559system.cpu.dcache.avg_refs 21.578431 # Average number of references to valid blocks.

560system.cpu.dcache.avg_refs 21.627451 # Average number of references to valid blocks.

560system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

561system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

561system.cpu.dcache.occ_blocks::cpu.data 63.058180 # Average occupied blocks per requestor
562system.cpu.dcache.occ_percent::cpu.data 0.015395 # Average percentage of cache occupancy
563system.cpu.dcache.occ_percent::total 0.015395 # Average percentage of cache occupancy
564system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits
565system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits
566system.cpu.dcache.WriteReq_hits::cpu.data 718 # number of WriteReq hits
567system.cpu.dcache.WriteReq_hits::total 718 # number of WriteReq hits
568system.cpu.dcache.demand_hits::cpu.data 2201 # number of demand (read+write) hits
569system.cpu.dcache.demand_hits::total 2201 # number of demand (read+write) hits
570system.cpu.dcache.overall_hits::cpu.data 2201 # number of overall hits
571system.cpu.dcache.overall_hits::total 2201 # number of overall hits
572system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses
573system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses
574system.cpu.dcache.WriteReq_misses::cpu.data 328 # number of WriteReq misses
575system.cpu.dcache.WriteReq_misses::total 328 # number of WriteReq misses
576system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses
577system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses
578system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses
579system.cpu.dcache.overall_misses::total 420 # number of overall misses
580system.cpu.dcache.ReadReq_miss_latency::cpu.data 3276500 # number of ReadReq miss cycles
581system.cpu.dcache.ReadReq_miss_latency::total 3276500 # number of ReadReq miss cycles
582system.cpu.dcache.WriteReq_miss_latency::cpu.data 9157000 # number of WriteReq miss cycles
583system.cpu.dcache.WriteReq_miss_latency::total 9157000 # number of WriteReq miss cycles
584system.cpu.dcache.demand_miss_latency::cpu.data 12433500 # number of demand (read+write) miss cycles
585system.cpu.dcache.demand_miss_latency::total 12433500 # number of demand (read+write) miss cycles
586system.cpu.dcache.overall_miss_latency::cpu.data 12433500 # number of overall miss cycles
587system.cpu.dcache.overall_miss_latency::total 12433500 # number of overall miss cycles
588system.cpu.dcache.ReadReq_accesses::cpu.data 1575 # number of ReadReq accesses(hits+misses)
589system.cpu.dcache.ReadReq_accesses::total 1575 # number of ReadReq accesses(hits+misses)

562system.cpu.dcache.occ_blocks::cpu.data 63.108123 # Average occupied blocks per requestor
563system.cpu.dcache.occ_percent::cpu.data 0.015407 # Average percentage of cache occupancy
564system.cpu.dcache.occ_percent::total 0.015407 # Average percentage of cache occupancy
565system.cpu.dcache.ReadReq_hits::cpu.data 1490 # number of ReadReq hits
566system.cpu.dcache.ReadReq_hits::total 1490 # number of ReadReq hits
567system.cpu.dcache.WriteReq_hits::cpu.data 716 # number of WriteReq hits
568system.cpu.dcache.WriteReq_hits::total 716 # number of WriteReq hits
569system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits
570system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits
571system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits
572system.cpu.dcache.overall_hits::total 2206 # number of overall hits
573system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
574system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
575system.cpu.dcache.WriteReq_misses::cpu.data 330 # number of WriteReq misses
576system.cpu.dcache.WriteReq_misses::total 330 # number of WriteReq misses
577system.cpu.dcache.demand_misses::cpu.data 427 # number of demand (read+write) misses
578system.cpu.dcache.demand_misses::total 427 # number of demand (read+write) misses
579system.cpu.dcache.overall_misses::cpu.data 427 # number of overall misses
580system.cpu.dcache.overall_misses::total 427 # number of overall misses
581system.cpu.dcache.ReadReq_miss_latency::cpu.data 4870000 # number of ReadReq miss cycles
582system.cpu.dcache.ReadReq_miss_latency::total 4870000 # number of ReadReq miss cycles
583system.cpu.dcache.WriteReq_miss_latency::cpu.data 14038497 # number of WriteReq miss cycles
584system.cpu.dcache.WriteReq_miss_latency::total 14038497 # number of WriteReq miss cycles
585system.cpu.dcache.demand_miss_latency::cpu.data 18908497 # number of demand (read+write) miss cycles
586system.cpu.dcache.demand_miss_latency::total 18908497 # number of demand (read+write) miss cycles
587system.cpu.dcache.overall_miss_latency::cpu.data 18908497 # number of overall miss cycles
588system.cpu.dcache.overall_miss_latency::total 18908497 # number of overall miss cycles
589system.cpu.dcache.ReadReq_accesses::cpu.data 1587 # number of ReadReq accesses(hits+misses)
590system.cpu.dcache.ReadReq_accesses::total 1587 # number of ReadReq accesses(hits+misses)

590system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
591system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)

591system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
592system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)

592system.cpu.dcache.demand_accesses::cpu.data 2621 # number of demand (read+write) accesses
593system.cpu.dcache.demand_accesses::total 2621 # number of demand (read+write) accesses
594system.cpu.dcache.overall_accesses::cpu.data 2621 # number of overall (read+write) accesses
595system.cpu.dcache.overall_accesses::total 2621 # number of overall (read+write) accesses
596system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058413 # miss rate for ReadReq accesses
597system.cpu.dcache.ReadReq_miss_rate::total 0.058413 # miss rate for ReadReq accesses
598system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.313576 # miss rate for WriteReq accesses
599system.cpu.dcache.WriteReq_miss_rate::total 0.313576 # miss rate for WriteReq accesses
600system.cpu.dcache.demand_miss_rate::cpu.data 0.160244 # miss rate for demand accesses
601system.cpu.dcache.demand_miss_rate::total 0.160244 # miss rate for demand accesses
602system.cpu.dcache.overall_miss_rate::cpu.data 0.160244 # miss rate for overall accesses
603system.cpu.dcache.overall_miss_rate::total 0.160244 # miss rate for overall accesses
604system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35614.130435 # average ReadReq miss latency
605system.cpu.dcache.ReadReq_avg_miss_latency::total 35614.130435 # average ReadReq miss latency
606system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27917.682927 # average WriteReq miss latency
607system.cpu.dcache.WriteReq_avg_miss_latency::total 27917.682927 # average WriteReq miss latency
608system.cpu.dcache.demand_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency
609system.cpu.dcache.demand_avg_miss_latency::total 29603.571429 # average overall miss latency
610system.cpu.dcache.overall_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency
611system.cpu.dcache.overall_avg_miss_latency::total 29603.571429 # average overall miss latency
612system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

593system.cpu.dcache.demand_accesses::cpu.data 2633 # number of demand (read+write) accesses
594system.cpu.dcache.demand_accesses::total 2633 # number of demand (read+write) accesses
595system.cpu.dcache.overall_accesses::cpu.data 2633 # number of overall (read+write) accesses
596system.cpu.dcache.overall_accesses::total 2633 # number of overall (read+write) accesses
597system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061122 # miss rate for ReadReq accesses
598system.cpu.dcache.ReadReq_miss_rate::total 0.061122 # miss rate for ReadReq accesses
599system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315488 # miss rate for WriteReq accesses
600system.cpu.dcache.WriteReq_miss_rate::total 0.315488 # miss rate for WriteReq accesses
601system.cpu.dcache.demand_miss_rate::cpu.data 0.162172 # miss rate for demand accesses
602system.cpu.dcache.demand_miss_rate::total 0.162172 # miss rate for demand accesses
603system.cpu.dcache.overall_miss_rate::cpu.data 0.162172 # miss rate for overall accesses
604system.cpu.dcache.overall_miss_rate::total 0.162172 # miss rate for overall accesses
605system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.185567 # average ReadReq miss latency
606system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.185567 # average ReadReq miss latency
607system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42540.900000 # average WriteReq miss latency
608system.cpu.dcache.WriteReq_avg_miss_latency::total 42540.900000 # average WriteReq miss latency
609system.cpu.dcache.demand_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency
610system.cpu.dcache.demand_avg_miss_latency::total 44282.194379 # average overall miss latency
611system.cpu.dcache.overall_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency
612system.cpu.dcache.overall_avg_miss_latency::total 44282.194379 # average overall miss latency
613system.cpu.dcache.blocked_cycles::no_mshrs 416 # number of cycles access was blocked

613system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

614system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

614system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked

615system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked

615system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

616system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

616system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

617system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.200000 # average number of cycles each access was blocked

617system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
618system.cpu.dcache.fast_writes 0 # number of fast writes performed
619system.cpu.dcache.cache_copies 0 # number of cache copies performed

618system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
619system.cpu.dcache.fast_writes 0 # number of fast writes performed
620system.cpu.dcache.cache_copies 0 # number of cache copies performed

620system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits
621system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits
622system.cpu.dcache.WriteReq_mshr_hits::cpu.data 281 # number of WriteReq MSHR hits
623system.cpu.dcache.WriteReq_mshr_hits::total 281 # number of WriteReq MSHR hits
624system.cpu.dcache.demand_mshr_hits::cpu.data 318 # number of demand (read+write) MSHR hits
625system.cpu.dcache.demand_mshr_hits::total 318 # number of demand (read+write) MSHR hits
626system.cpu.dcache.overall_mshr_hits::cpu.data 318 # number of overall MSHR hits
627system.cpu.dcache.overall_mshr_hits::total 318 # number of overall MSHR hits

621system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
622system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
623system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits
624system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits
625system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits
626system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
627system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits
628system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits

628system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
629system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
630system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
631system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
632system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
633system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
634system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
635system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses

629system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
630system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
631system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
632system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
633system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
634system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
635system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
636system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses

636system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2135500 # number of ReadReq MSHR miss cycles
637system.cpu.dcache.ReadReq_mshr_miss_latency::total 2135500 # number of ReadReq MSHR miss cycles
638system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2069500 # number of WriteReq MSHR miss cycles
639system.cpu.dcache.WriteReq_mshr_miss_latency::total 2069500 # number of WriteReq MSHR miss cycles
640system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4205000 # number of demand (read+write) MSHR miss cycles
641system.cpu.dcache.demand_mshr_miss_latency::total 4205000 # number of demand (read+write) MSHR miss cycles
642system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4205000 # number of overall MSHR miss cycles
643system.cpu.dcache.overall_mshr_miss_latency::total 4205000 # number of overall MSHR miss cycles
644system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034921 # mshr miss rate for ReadReq accesses
645system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034921 # mshr miss rate for ReadReq accesses

637system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3072500 # number of ReadReq MSHR miss cycles
638system.cpu.dcache.ReadReq_mshr_miss_latency::total 3072500 # number of ReadReq MSHR miss cycles
639system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2817999 # number of WriteReq MSHR miss cycles
640system.cpu.dcache.WriteReq_mshr_miss_latency::total 2817999 # number of WriteReq MSHR miss cycles
641system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5890499 # number of demand (read+write) MSHR miss cycles
642system.cpu.dcache.demand_mshr_miss_latency::total 5890499 # number of demand (read+write) MSHR miss cycles
643system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5890499 # number of overall MSHR miss cycles
644system.cpu.dcache.overall_mshr_miss_latency::total 5890499 # number of overall MSHR miss cycles
645system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034657 # mshr miss rate for ReadReq accesses
646system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034657 # mshr miss rate for ReadReq accesses

646system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
647system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses

647system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
648system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses

648system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038916 # mshr miss rate for demand accesses
649system.cpu.dcache.demand_mshr_miss_rate::total 0.038916 # mshr miss rate for demand accesses
650system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038916 # mshr miss rate for overall accesses
651system.cpu.dcache.overall_mshr_miss_rate::total 0.038916 # mshr miss rate for overall accesses
652system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38827.272727 # average ReadReq mshr miss latency
653system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38827.272727 # average ReadReq mshr miss latency
654system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44031.914894 # average WriteReq mshr miss latency
655system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44031.914894 # average WriteReq mshr miss latency
656system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41225.490196 # average overall mshr miss latency
657system.cpu.dcache.demand_avg_mshr_miss_latency::total 41225.490196 # average overall mshr miss latency
658system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41225.490196 # average overall mshr miss latency
659system.cpu.dcache.overall_avg_mshr_miss_latency::total 41225.490196 # average overall mshr miss latency

649system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for demand accesses
650system.cpu.dcache.demand_mshr_miss_rate::total 0.038739 # mshr miss rate for demand accesses
651system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for overall accesses
652system.cpu.dcache.overall_mshr_miss_rate::total 0.038739 # mshr miss rate for overall accesses
653system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55863.636364 # average ReadReq mshr miss latency
654system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55863.636364 # average ReadReq mshr miss latency
655system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59957.425532 # average WriteReq mshr miss latency
656system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59957.425532 # average WriteReq mshr miss latency
657system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency
658system.cpu.dcache.demand_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency
659system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency
660system.cpu.dcache.overall_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency

660system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
661system.cpu.l2cache.replacements 0 # number of replacements

661system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
662system.cpu.l2cache.replacements 0 # number of replacements

662system.cpu.l2cache.tagsinuse 202.511775 # Cycle average of tags in use

663system.cpu.l2cache.tagsinuse 202.387362 # Cycle average of tags in use

663system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.

664system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.

664system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
665system.cpu.l2cache.avg_refs 0.012285 # Average number of references to valid blocks.

665system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks.
666system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks.

666system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

667system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

667system.cpu.l2cache.occ_blocks::cpu.inst 171.159478 # Average occupied blocks per requestor
668system.cpu.l2cache.occ_blocks::cpu.data 31.352298 # Average occupied blocks per requestor
669system.cpu.l2cache.occ_percent::cpu.inst 0.005223 # Average percentage of cache occupancy
670system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy
671system.cpu.l2cache.occ_percent::total 0.006180 # Average percentage of cache occupancy

668system.cpu.l2cache.occ_blocks::cpu.inst 170.963901 # Average occupied blocks per requestor
669system.cpu.l2cache.occ_blocks::cpu.data 31.423461 # Average occupied blocks per requestor
670system.cpu.l2cache.occ_percent::cpu.inst 0.005217 # Average percentage of cache occupancy
671system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy
672system.cpu.l2cache.occ_percent::total 0.006176 # Average percentage of cache occupancy

672system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
673system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
674system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
675system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
676system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
677system.cpu.l2cache.overall_hits::total 5 # number of overall hits

673system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
674system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
675system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
676system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
677system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
678system.cpu.l2cache.overall_hits::total 5 # number of overall hits

678system.cpu.l2cache.ReadReq_misses::cpu.inst 352 # number of ReadReq misses

679system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses

679system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses

680system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses

680system.cpu.l2cache.ReadReq_misses::total 407 # number of ReadReq misses

681system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses

681system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
682system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses

682system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
683system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses

683system.cpu.l2cache.demand_misses::cpu.inst 352 # number of demand (read+write) misses

684system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses

684system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses

685system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses

685system.cpu.l2cache.demand_misses::total 454 # number of demand (read+write) misses
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