| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11243500 # Number of ticks simulated 5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11243500 # Number of ticks simulated 5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 73653 # Simulator instruction rate (inst/s) 8host_op_rate 73641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 142731766 # Simulator tick rate (ticks/s) 10host_mem_usage 211540 # Number of bytes of host memory used | 7host_inst_rate 72271 # Simulator instruction rate (inst/s) 8host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 140039967 # Simulator tick rate (ticks/s) 10host_mem_usage 211876 # Number of bytes of host memory used |
| 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5800 # Number of instructions simulated 13sim_ops 5800 # Number of ops (including micro ops) simulated | 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5800 # Number of instructions simulated 13sim_ops 5800 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 28736 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 449 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.read_accesses 0 # DTB read accesses 26system.cpu.dtb.write_hits 0 # DTB write hits 27system.cpu.dtb.write_misses 0 # DTB write misses 28system.cpu.dtb.write_accesses 0 # DTB write accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses --- 303 unchanged lines hidden (view full) --- 334system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles 335system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) 336system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) 337system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses 338system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses 339system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses 340system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses 341system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses | 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses --- 303 unchanged lines hidden (view full) --- 341system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles 342system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) 343system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) 344system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses 345system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses 346system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses 347system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses 348system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses |
| 349system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses |
|
| 342system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses | 350system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses |
| 351system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses |
|
| 343system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses | 352system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses |
| 353system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses |
|
| 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency | 354system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency |
| 355system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency |
|
| 345system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency | 356system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency |
| 357system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency |
|
| 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency | 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency |
| 359system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency |
|
| 347system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 348system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 351system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 352system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 353system.cpu.icache.fast_writes 0 # number of fast writes performed 354system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 366system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses 367system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles 368system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles 369system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles 373system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses | 360system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.icache.fast_writes 0 # number of fast writes performed 367system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 379system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses 380system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles 381system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles 382system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles 383system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles 384system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles 385system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles 386system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses |
| 387system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses |
|
| 374system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses | 388system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses |
| 389system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses |
|
| 375system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses | 390system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses |
| 391system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses |
|
| 376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency | 392system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency |
| 393system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency |
|
| 377system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency | 394system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency |
| 395system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency |
|
| 378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency | 396system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency |
| 397system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency |
|
| 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 380system.cpu.dcache.replacements 0 # number of replacements 381system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use 382system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. 383system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. 384system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. 385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 386system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 414system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) 415system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 417system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses 418system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses 419system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses 420system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses 421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses | 398system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 399system.cpu.dcache.replacements 0 # number of replacements 400system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use 401system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. 402system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. 403system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. 404system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 405system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 433system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 436system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses 437system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses 438system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses 439system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses 440system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses |
| 441system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses |
|
| 422system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses | 442system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses |
| 443system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses |
|
| 423system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses | 444system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses |
| 445system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses |
|
| 424system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses | 446system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses |
| 447system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses |
|
| 425system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency | 448system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency |
| 449system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency |
|
| 426system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency | 450system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency |
| 451system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency |
|
| 427system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency | 452system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency |
| 453system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency |
|
| 428system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency | 454system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency |
| 455system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency |
|
| 429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 433system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 434system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 435system.cpu.dcache.fast_writes 0 # number of fast writes performed 436system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 454system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles 455system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles 456system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles 457system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles 458system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles 459system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles 460system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles 461system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses | 456system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 457system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 458system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 460system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 461system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 462system.cpu.dcache.fast_writes 0 # number of fast writes performed 463system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 481system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles 487system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles 488system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses |
| 489system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses |
|
| 462system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses | 490system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses |
| 491system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses |
|
| 463system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses | 492system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses |
| 493system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses |
|
| 464system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses | 494system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses |
| 495system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses |
|
| 465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency | 496system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency |
| 497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency |
|
| 466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency | 498system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency |
| 499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency |
|
| 467system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency | 500system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency |
| 501system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency |
|
| 468system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency | 502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency |
| 503system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency |
|
| 469system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 470system.cpu.l2cache.replacements 0 # number of replacements 471system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use 472system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. 473system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. 474system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. 475system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 476system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 514system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses 515system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses 516system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses 517system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses 518system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses 519system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses 520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses 521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 504system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 505system.cpu.l2cache.replacements 0 # number of replacements 506system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use 507system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. 508system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. 509system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. 510system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 511system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 549system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses 555system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 557system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses |
|
| 522system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses | 558system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 559system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
|
| 523system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses 524system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 560system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses 561system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 562system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses |
|
| 525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses 526system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 563system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses 564system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 565system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses |
|
| 527system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency 528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency | 566system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency 567system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency |
| 568system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency |
|
| 529system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency | 569system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency |
| 570system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency |
|
| 530system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 531system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency | 571system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 572system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency |
| 573system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency |
|
| 532system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency | 574system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 575system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency |
| 576system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency |
|
| 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles 564system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses 565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 577system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 583system.cpu.l2cache.fast_writes 0 # number of fast writes performed 584system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 601system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles 602system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles 603system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles 604system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles 605system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles 606system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles 607system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses 608system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 609system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses |
|
| 566system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses | 610system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 611system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
|
| 567system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses 568system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 612system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses 613system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 614system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses |
|
| 569system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses 570system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 615system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses 616system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 617system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses |
|
| 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency | 618system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency 619system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency |
| 620system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency |
|
| 573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency | 621system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency |
| 622system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency |
|
| 574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency | 623system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency |
| 625system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency |
|
| 576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency | 626system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency |
| 628system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency |
|
| 578system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 579 580---------- End Simulation Statistics ---------- | 629system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 630 631---------- End Simulation Statistics ---------- |