| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11243500 # Number of ticks simulated 5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11243500 # Number of ticks simulated 5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 108078 # Simulator instruction rate (inst/s) 8host_op_rate 108043 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 209380098 # Simulator tick rate (ticks/s) 10host_mem_usage 207884 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 73653 # Simulator instruction rate (inst/s) 8host_op_rate 73641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 142731766 # Simulator tick rate (ticks/s) 10host_mem_usage 211540 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 5800 # Number of instructions simulated 13sim_ops 5800 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28736 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 449 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 323 unchanged lines hidden (view full) --- 343system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency 345system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 347system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 348system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 5800 # Number of instructions simulated 13sim_ops 5800 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28736 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 449 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 323 unchanged lines hidden (view full) --- 343system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency 345system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 347system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 348system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 351system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 352system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 351system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 352system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 353system.cpu.icache.fast_writes 0 # number of fast writes performed 354system.cpu.icache.cache_copies 0 # number of cache copies performed 355system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits 356system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 357system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits 358system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits 359system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits 360system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 425system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency 426system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency 427system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 428system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 353system.cpu.icache.fast_writes 0 # number of fast writes performed 354system.cpu.icache.cache_copies 0 # number of cache copies performed 355system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits 356system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 357system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits 358system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits 359system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits 360system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 425system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency 426system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency 427system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 428system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 433system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 434system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 433system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 434system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 435system.cpu.dcache.fast_writes 0 # number of fast writes performed 436system.cpu.dcache.cache_copies 0 # number of cache copies performed 437system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits 438system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits 439system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits 440system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits 441system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits 442system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 530system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 531system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 435system.cpu.dcache.fast_writes 0 # number of fast writes performed 436system.cpu.dcache.cache_copies 0 # number of cache copies performed 437system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits 438system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits 439system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits 440system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits 441system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits 442system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 530system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 531system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed 542system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses 546system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses 547system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed 542system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses 546system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses 547system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |