| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated |
| 4sim_ticks 21268000 # Number of ticks simulated 5final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 21189000 # Number of ticks simulated 5final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 49400 # Simulator instruction rate (inst/s) 8host_op_rate 49392 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 181337178 # Simulator tick rate (ticks/s) 10host_mem_usage 231948 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host | 7host_inst_rate 143245 # Simulator instruction rate (inst/s) 8host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 523712790 # Simulator tick rate (ticks/s) 10host_mem_usage 249592 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory | 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory | 20system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::total 443 # Number of read requests responded to by this memory | 24system.physmem.num_reads::total 443 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 1032160993 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 300921572 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1333082565 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1032160993 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1032160993 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1032160993 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 300921572 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1333082565 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 445 # Number of read requests accepted | 25system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 444 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 71 # Per bank write bursts 46system.physmem.perBankRdBursts::1 42 # Per bank write bursts 47system.physmem.perBankRdBursts::2 55 # Per bank write bursts 48system.physmem.perBankRdBursts::3 58 # Per bank write bursts 49system.physmem.perBankRdBursts::4 53 # Per bank write bursts | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 71 # Per bank write bursts 46system.physmem.perBankRdBursts::1 42 # Per bank write bursts 47system.physmem.perBankRdBursts::2 55 # Per bank write bursts 48system.physmem.perBankRdBursts::3 58 # Per bank write bursts 49system.physmem.perBankRdBursts::4 53 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::5 62 # Per bank write bursts | 50system.physmem.perBankRdBursts::5 61 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::6 52 # Per bank write bursts 52system.physmem.perBankRdBursts::7 10 # Per bank write bursts 53system.physmem.perBankRdBursts::8 9 # Per bank write bursts 54system.physmem.perBankRdBursts::9 28 # Per bank write bursts 55system.physmem.perBankRdBursts::10 1 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 0 # Per bank write bursts 58system.physmem.perBankRdBursts::13 0 # Per bank write bursts --- 12 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 51system.physmem.perBankRdBursts::6 52 # Per bank write bursts 52system.physmem.perBankRdBursts::7 10 # Per bank write bursts 53system.physmem.perBankRdBursts::8 9 # Per bank write bursts 54system.physmem.perBankRdBursts::9 28 # Per bank write bursts 55system.physmem.perBankRdBursts::10 1 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 0 # Per bank write bursts 58system.physmem.perBankRdBursts::13 0 # Per bank write bursts --- 12 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 21217500 # Total gap between requests | 79system.physmem.totGap 21128500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 445 # Read request sizes (log2) | 86system.physmem.readPktSize::6 444 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 351.573333 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 215.062906 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 340.509998 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 23 30.67% 30.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 18 24.00% 54.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 11 14.67% 69.33% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 2 2.67% 72.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 4.00% 76.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 5.33% 81.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.67% 84.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 4.00% 88.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 12.00% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation 204system.physmem.totQLat 5980000 # Total ticks spent queuing 205system.physmem.totMemAccLat 14323750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13438.20 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation 204system.physmem.totQLat 5920000 # Total ticks spent queuing 205system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 32188.20 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1339.10 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1339.10 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 10.46 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.46 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 10.48 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 360 # Number of row buffer hits during reads | 220system.physmem.readRowHits 358 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 47679.78 # Average gap between requests 225system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 47586.71 # Average gap between requests 225system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) | 228system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3922170 # Energy for active background per rank (pJ) | 231system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 5666370 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) | 233system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 14570505 # Total energy per rank (pJ) 237system.physmem_0.averagePower 685.066353 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 12593250 # Total Idle time Per DRAM Rank | 236system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) 237system.physmem_0.averagePower 685.810052 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 167250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 8137250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 12426000 # Time in different power states 245system.physmem_1.actEnergy 78540 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 30360 # Energy for precharge commands per rank (pJ) | 242system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states 245system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) |
| 247system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 247system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 747840 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 1408800 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6431880 # Energy for active power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) |
| 253system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 253system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 10938900 # Total energy per rank (pJ) 256system.physmem_1.averagePower 514.317955 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 13775500 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 3585000 # Time in different power states | 255system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) 256system.physmem_1.averagePower 515.021000 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states |
| 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states |
| 262system.physmem_1.memoryStateTime::ACT 1201500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 14106750 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2411 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1982 # Number of conditional branches predicted | 262system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2458 # Number of BP lookups 266system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted |
| 267system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect | 267system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect |
| 268system.cpu.branchPred.BTBLookups 2056 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 693 # Number of BTB hits | 268system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 724 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 33.706226 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 19 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 111 # Number of indirect misses. | 271system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. |
| 277system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 9 # Number of system calls | 277system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 9 # Number of system calls |
| 298system.cpu.pwrStateResidencyTicks::ON 21268000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 42537 # number of cpu cycles simulated | 298system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 42379 # number of cpu cycles simulated |
| 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 302system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 4149 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 849 # Number of cycles fetch has spent squashing | 302system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing |
| 308system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps 310system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR | 308system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps 310system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR |
| 311system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched 312system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed 313system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched 312system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed 313system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) |
| 316system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 317system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total) | 317system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) |
| 326system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 329system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle 331system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle 332system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle 333system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked 334system.cpu.decode.RunCycles 1946 # Number of cycles decode is running | 329system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle 331system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle 332system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle 333system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked 334system.cpu.decode.RunCycles 1957 # Number of cycles decode is running |
| 335system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking | 335system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking |
| 336system.cpu.decode.SquashCycles 276 # Number of cycles decode is squashing 337system.cpu.decode.BranchResolved 324 # Number of times decode resolved a branch | 336system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing 337system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch |
| 338system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction | 338system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction |
| 339system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode 340system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode 341system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing 342system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle 343system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking 344system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst 345system.cpu.rename.RunCycles 1897 # Number of cycles rename is running 346system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking 347system.cpu.rename.RenamedInsts 11042 # Number of instructions processed by rename 348system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full | 339system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode 340system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode 341system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing 342system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle 343system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking 344system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst 345system.cpu.rename.RunCycles 1904 # Number of cycles rename is running 346system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking 347system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename 348system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full |
| 349system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full | 349system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full |
| 350system.cpu.rename.SQFullEvents 1522 # Number of times rename has blocked due to SQ full 351system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed 352system.cpu.rename.RenameLookups 17897 # Number of register rename lookups that rename has made 353system.cpu.rename.int_rename_lookups 17871 # Number of integer rename lookups | 350system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full 351system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed 352system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made 353system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups |
| 354system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 355system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed | 354system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 355system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed |
| 356system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing | 356system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing |
| 357system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 358system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 357system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 358system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 359system.cpu.rename.skidInsts 381 # count of insts added to the skid buffer 360system.cpu.memDep0.insertedLoads 1937 # Number of loads inserted to the mem dependence unit. 361system.cpu.memDep0.insertedStores 1590 # Number of stores inserted to the mem dependence unit. | 359system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer 360system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. 361system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. |
| 362system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. | 362system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. |
| 363system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. 364system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ 366system.cpu.iq.iqInstsIssued 8808 # Number of instructions issued 367system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued 368system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling 369system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph 370system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed 371system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle | 363system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. 364system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ 366system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued 367system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued 368system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling 369system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph 370system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed 371system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 375system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::4 429 3.45% 95.18% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::5 293 2.36% 97.54% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::6 212 1.71% 99.24% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::7 64 0.52% 99.76% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Number of insts issued each cycle | 375system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle |
| 384system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 384system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 387system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle | 387system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle |
| 388system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 388system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 389system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.06% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemRead 88 44.44% 50.51% # attempts to use FU when none available 421system.cpu.iq.fu_full::MemWrite 87 43.94% 94.44% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.44% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatMemWrite 11 5.56% 100.00% # attempts to use FU when none available | 389system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available 421system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available |
| 424system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 424system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 427system.cpu.iq.FU_type_0::IntAlu 5530 62.78% 62.78% # Type of FU issued 428system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued 429system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.81% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.81% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.81% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.81% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.81% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.81% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.81% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.81% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.81% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.81% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.81% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.81% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.81% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.81% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.81% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.81% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued 458system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.37% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 1439 16.34% 99.70% # Type of FU issued | 427system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued 428system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued 429system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued 458system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued |
| 460system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued 461system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 460system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued 461system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::total 8808 # Type of FU issued 465system.cpu.iq.rate 0.207067 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 198 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses | 464system.cpu.iq.FU_type_0::total 8807 # Type of FU issued 465system.cpu.iq.rate 0.207815 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 193 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses |
| 471system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses | 471system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses |
| 474system.cpu.iq.int_alu_accesses 8967 # Number of integer alu accesses | 474system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses |
| 475system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses | 475system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses |
| 476system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores | 476system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores |
| 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 478system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 544 # Number of stores squashed | 478system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed |
| 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 485system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked | 485system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked |
| 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 487system.cpu.iew.iewSquashCycles 276 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 722 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 71 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 1937 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 1590 # Number of dispatched store instructions | 487system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions |
| 494system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall | 494system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall |
| 497system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly | 497system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly |
| 499system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly | 499system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly |
| 500system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 8463 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 1703 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 345 # Number of squashed instructions skipped in execute | 500system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute |
| 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed | 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 506system.cpu.iew.exec_refs 3080 # number of memory reference insts executed 507system.cpu.iew.exec_branches 1358 # Number of branches executed 508system.cpu.iew.exec_stores 1377 # Number of stores executed 509system.cpu.iew.exec_rate 0.198956 # Inst execution rate 510system.cpu.iew.wb_sent 8242 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 8142 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 4448 # num instructions producing a value 513system.cpu.iew.wb_consumers 7158 # num instructions consuming a value 514system.cpu.iew.wb_rate 0.191410 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.621403 # average fanout of values written-back 516system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit | 506system.cpu.iew.exec_refs 3083 # number of memory reference insts executed 507system.cpu.iew.exec_branches 1364 # Number of branches executed 508system.cpu.iew.exec_stores 1364 # Number of stores executed 509system.cpu.iew.exec_rate 0.200288 # Inst execution rate 510system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 8160 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 4466 # num instructions producing a value 513system.cpu.iew.wb_consumers 7207 # num instructions consuming a value 514system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back 516system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit |
| 517system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 518system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted | 517system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 518system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted |
| 519system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle | 519system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle |
| 522system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 523system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle | 523system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle |
| 532system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 532system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 535system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle | 535system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle |
| 536system.cpu.commit.committedInsts 5792 # Number of instructions committed 537system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 538system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 539system.cpu.commit.refs 2007 # Number of memory references committed 540system.cpu.commit.loads 961 # Number of loads committed 541system.cpu.commit.membars 7 # Number of memory barriers committed 542system.cpu.commit.branches 1037 # Number of branches committed 543system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 577system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 578system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction 579system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction 580system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction 581system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction 582system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::total 5792 # Class of committed instruction | 536system.cpu.commit.committedInsts 5792 # Number of instructions committed 537system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 538system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 539system.cpu.commit.refs 2007 # Number of memory references committed 540system.cpu.commit.loads 961 # Number of loads committed 541system.cpu.commit.membars 7 # Number of memory barriers committed 542system.cpu.commit.branches 1037 # Number of branches committed 543system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 577system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 578system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction 579system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction 580system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction 581system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction 582system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::total 5792 # Class of committed instruction |
| 585system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached 586system.cpu.rob.rob_reads 21844 # The number of ROB reads 587system.cpu.rob.rob_writes 21175 # The number of ROB writes 588system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 589system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling | 585system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached 586system.cpu.rob.rob_reads 21974 # The number of ROB reads 587system.cpu.rob.rob_writes 21247 # The number of ROB writes 588system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself 589system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 590system.cpu.committedInsts 5792 # Number of Instructions Simulated 591system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated | 590system.cpu.committedInsts 5792 # Number of Instructions Simulated 591system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated |
| 592system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction 593system.cpu.cpi_total 7.344095 # CPI: Total CPI of All Threads 594system.cpu.ipc 0.136164 # IPC: Instructions Per Cycle 595system.cpu.ipc_total 0.136164 # IPC: Total IPC of All Threads 596system.cpu.int_regfile_reads 13368 # number of integer regfile reads 597system.cpu.int_regfile_writes 7153 # number of integer regfile writes | 592system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction 593system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads 594system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle 595system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads 596system.cpu.int_regfile_reads 13468 # number of integer regfile reads 597system.cpu.int_regfile_writes 7187 # number of integer regfile writes |
| 598system.cpu.fp_regfile_reads 25 # number of floating regfile reads 599system.cpu.fp_regfile_writes 2 # number of floating regfile writes | 598system.cpu.fp_regfile_reads 25 # number of floating regfile reads 599system.cpu.fp_regfile_writes 2 # number of floating regfile writes |
| 600system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states | 600system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states |
| 601system.cpu.dcache.tags.replacements 0 # number of replacements | 601system.cpu.dcache.tags.replacements 0 # number of replacements |
| 602system.cpu.dcache.tags.tagsinuse 64.389343 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 2206 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 21.627451 # Average number of references to valid blocks. | 602system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. |
| 606system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 606system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 607system.cpu.dcache.tags.occ_blocks::cpu.data 64.389343 # Average occupied blocks per requestor 608system.cpu.dcache.tags.occ_percent::cpu.data 0.015720 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.015720 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 613system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 614system.cpu.dcache.tags.tag_accesses 5390 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 5390 # Number of data accesses 616system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.ReadReq_hits::cpu.data 1485 # number of ReadReq hits 618system.cpu.dcache.ReadReq_hits::total 1485 # number of ReadReq hits | 607system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor 608system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id 613system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id 614system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses 616system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits 618system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits |
| 619system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits 620system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits | 619system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits 620system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits |
| 621system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits 622system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits 623system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits 624system.cpu.dcache.overall_hits::total 2206 # number of overall hits 625system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 626system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses | 621system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits 622system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits 623system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits 624system.cpu.dcache.overall_hits::total 2204 # number of overall hits 625system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses 626system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses |
| 627system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses 628system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses | 627system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses 628system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses |
| 629system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses 630system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses 631system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses 632system.cpu.dcache.overall_misses::total 438 # number of overall misses 633system.cpu.dcache.ReadReq_miss_latency::cpu.data 8211000 # number of ReadReq miss cycles 634system.cpu.dcache.ReadReq_miss_latency::total 8211000 # number of ReadReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::cpu.data 32489496 # number of WriteReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::total 32489496 # number of WriteReq miss cycles 637system.cpu.dcache.demand_miss_latency::cpu.data 40700496 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 40700496 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 40700496 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 40700496 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 1598 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) | 629system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses 630system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses 631system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses 632system.cpu.dcache.overall_misses::total 437 # number of overall misses 633system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles 634system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles 637system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 40627496 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 40627496 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 40627496 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 1595 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 1595 # number of ReadReq accesses(hits+misses) |
| 643system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) | 643system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) |
| 645system.cpu.dcache.demand_accesses::cpu.data 2644 # number of demand (read+write) accesses 646system.cpu.dcache.demand_accesses::total 2644 # number of demand (read+write) accesses 647system.cpu.dcache.overall_accesses::cpu.data 2644 # number of overall (read+write) accesses 648system.cpu.dcache.overall_accesses::total 2644 # number of overall (read+write) accesses 649system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070713 # miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_miss_rate::total 0.070713 # miss rate for ReadReq accesses | 645system.cpu.dcache.demand_accesses::cpu.data 2641 # number of demand (read+write) accesses 646system.cpu.dcache.demand_accesses::total 2641 # number of demand (read+write) accesses 647system.cpu.dcache.overall_accesses::cpu.data 2641 # number of overall (read+write) accesses 648system.cpu.dcache.overall_accesses::total 2641 # number of overall (read+write) accesses 649system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070219 # miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_miss_rate::total 0.070219 # miss rate for ReadReq accesses |
| 651system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses | 651system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses |
| 653system.cpu.dcache.demand_miss_rate::cpu.data 0.165658 # miss rate for demand accesses 654system.cpu.dcache.demand_miss_rate::total 0.165658 # miss rate for demand accesses 655system.cpu.dcache.overall_miss_rate::cpu.data 0.165658 # miss rate for overall accesses 656system.cpu.dcache.overall_miss_rate::total 0.165658 # miss rate for overall accesses 657system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814 # average ReadReq miss latency 658system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814 # average ReadReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000 # average WriteReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000 # average WriteReq miss latency 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 92923.506849 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 92923.506849 # average overall miss latency 665system.cpu.dcache.blocked_cycles::no_mshrs 612 # number of cycles access was blocked | 653system.cpu.dcache.demand_miss_rate::cpu.data 0.165468 # miss rate for demand accesses 654system.cpu.dcache.demand_miss_rate::total 0.165468 # miss rate for demand accesses 655system.cpu.dcache.overall_miss_rate::cpu.data 0.165468 # miss rate for overall accesses 656system.cpu.dcache.overall_miss_rate::total 0.165468 # miss rate for overall accesses 657system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72584.821429 # average ReadReq miss latency 658system.cpu.dcache.ReadReq_avg_miss_latency::total 72584.821429 # average ReadReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99993.833846 # average WriteReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::total 99993.833846 # average WriteReq miss latency 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency 665system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked |
| 666system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 666system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 667system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked | 667system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked |
| 668system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 668system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 102 # average number of cycles each access was blocked | 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked |
| 670system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 670system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 671system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 672system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits | 671system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits 672system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits |
| 673system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits 674system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits | 673system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits 674system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits |
| 675system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits 676system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits 677system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits 678system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses | 675system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits 676system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits 677system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits 678system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses |
| 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses | 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses |
| 683system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4669500 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 4669500 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4693998 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 4693998 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9363498 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 9363498 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9363498 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 9363498 # number of overall MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035670 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035670 # mshr miss rate for ReadReq accesses | 683system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4818000 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 4818000 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4694498 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 4694498 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9512498 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 9512498 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9512498 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 9512498 # number of overall MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036364 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036364 # mshr miss rate for ReadReq accesses |
| 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses | 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses |
| 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.039334 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.039334 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632 # average ReadReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872 # average WriteReq mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency 711system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states | 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.039758 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.039758 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency 711system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states |
| 712system.cpu.icache.tags.replacements 0 # number of replacements | 712system.cpu.icache.tags.replacements 0 # number of replacements |
| 713system.cpu.icache.tags.tagsinuse 168.912200 # Cycle average of tags in use 714system.cpu.icache.tags.total_refs 1425 # Total number of references to valid blocks. | 713system.cpu.icache.tags.tagsinuse 168.700112 # Cycle average of tags in use 714system.cpu.icache.tags.total_refs 1435 # Total number of references to valid blocks. |
| 715system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. | 715system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. |
| 716system.cpu.icache.tags.avg_refs 4.083095 # Average number of references to valid blocks. | 716system.cpu.icache.tags.avg_refs 4.111748 # Average number of references to valid blocks. |
| 717system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 717system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 718system.cpu.icache.tags.occ_blocks::cpu.inst 168.912200 # Average occupied blocks per requestor 719system.cpu.icache.tags.occ_percent::cpu.inst 0.082477 # Average percentage of cache occupancy 720system.cpu.icache.tags.occ_percent::total 0.082477 # Average percentage of cache occupancy | 718system.cpu.icache.tags.occ_blocks::cpu.inst 168.700112 # Average occupied blocks per requestor 719system.cpu.icache.tags.occ_percent::cpu.inst 0.082373 # Average percentage of cache occupancy 720system.cpu.icache.tags.occ_percent::total 0.082373 # Average percentage of cache occupancy |
| 721system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id | 721system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id |
| 722system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id | 722system.cpu.icache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id |
| 724system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id | 724system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id |
| 725system.cpu.icache.tags.tag_accesses 4071 # Number of tag accesses 726system.cpu.icache.tags.data_accesses 4071 # Number of data accesses 727system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 728system.cpu.icache.ReadReq_hits::cpu.inst 1425 # number of ReadReq hits 729system.cpu.icache.ReadReq_hits::total 1425 # number of ReadReq hits 730system.cpu.icache.demand_hits::cpu.inst 1425 # number of demand (read+write) hits 731system.cpu.icache.demand_hits::total 1425 # number of demand (read+write) hits 732system.cpu.icache.overall_hits::cpu.inst 1425 # number of overall hits 733system.cpu.icache.overall_hits::total 1425 # number of overall hits 734system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses 735system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses 736system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses 737system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses 738system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses 739system.cpu.icache.overall_misses::total 436 # number of overall misses 740system.cpu.icache.ReadReq_miss_latency::cpu.inst 33901500 # number of ReadReq miss cycles 741system.cpu.icache.ReadReq_miss_latency::total 33901500 # number of ReadReq miss cycles 742system.cpu.icache.demand_miss_latency::cpu.inst 33901500 # number of demand (read+write) miss cycles 743system.cpu.icache.demand_miss_latency::total 33901500 # number of demand (read+write) miss cycles 744system.cpu.icache.overall_miss_latency::cpu.inst 33901500 # number of overall miss cycles 745system.cpu.icache.overall_miss_latency::total 33901500 # number of overall miss cycles 746system.cpu.icache.ReadReq_accesses::cpu.inst 1861 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.ReadReq_accesses::total 1861 # number of ReadReq accesses(hits+misses) 748system.cpu.icache.demand_accesses::cpu.inst 1861 # number of demand (read+write) accesses 749system.cpu.icache.demand_accesses::total 1861 # number of demand (read+write) accesses 750system.cpu.icache.overall_accesses::cpu.inst 1861 # number of overall (read+write) accesses 751system.cpu.icache.overall_accesses::total 1861 # number of overall (read+write) accesses 752system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234283 # miss rate for ReadReq accesses 753system.cpu.icache.ReadReq_miss_rate::total 0.234283 # miss rate for ReadReq accesses 754system.cpu.icache.demand_miss_rate::cpu.inst 0.234283 # miss rate for demand accesses 755system.cpu.icache.demand_miss_rate::total 0.234283 # miss rate for demand accesses 756system.cpu.icache.overall_miss_rate::cpu.inst 0.234283 # miss rate for overall accesses 757system.cpu.icache.overall_miss_rate::total 0.234283 # miss rate for overall accesses 758system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945 # average ReadReq miss latency 759system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945 # average ReadReq miss latency 760system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency 761system.cpu.icache.demand_avg_miss_latency::total 77755.733945 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency 763system.cpu.icache.overall_avg_miss_latency::total 77755.733945 # average overall miss latency 764system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked | 725system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses 726system.cpu.icache.tags.data_accesses 4079 # Number of data accesses 727system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 728system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits 729system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits 730system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits 731system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits 732system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits 733system.cpu.icache.overall_hits::total 1435 # number of overall hits 734system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses 735system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses 736system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses 737system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses 738system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses 739system.cpu.icache.overall_misses::total 430 # number of overall misses 740system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles 741system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles 742system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles 743system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles 744system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles 745system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles 746system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) 748system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses 749system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses 750system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses 751system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses 752system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses 753system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses 754system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses 755system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses 756system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses 757system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses 758system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency 759system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency 760system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency 761system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency 763system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency 764system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked |
| 765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 768system.cpu.icache.avg_blocked_cycles::no_mshrs 113.400000 # average number of cycles each access was blocked | 768system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked |
| 769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 770system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 771system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 772system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 773system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 774system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 775system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits | 770system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits 771system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 772system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits 773system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits 774system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits 775system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits |
| 776system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 777system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 778system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 779system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 780system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 781system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses | 776system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 777system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 778system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 779system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 780system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 781system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses |
| 782system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28298000 # number of ReadReq MSHR miss cycles 783system.cpu.icache.ReadReq_mshr_miss_latency::total 28298000 # number of ReadReq MSHR miss cycles 784system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28298000 # number of demand (read+write) MSHR miss cycles 785system.cpu.icache.demand_mshr_miss_latency::total 28298000 # number of demand (read+write) MSHR miss cycles 786system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28298000 # number of overall MSHR miss cycles 787system.cpu.icache.overall_mshr_miss_latency::total 28298000 # number of overall MSHR miss cycles 788system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for ReadReq accesses 789system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188071 # mshr miss rate for ReadReq accesses 790system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for demand accesses 791system.cpu.icache.demand_mshr_miss_rate::total 0.188071 # mshr miss rate for demand accesses 792system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for overall accesses 793system.cpu.icache.overall_mshr_miss_rate::total 0.188071 # mshr miss rate for overall accesses 794system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571 # average ReadReq mshr miss latency 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571 # average ReadReq mshr miss latency 796system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency 798system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency 800system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states | 782system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles 783system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles 784system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles 785system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles 786system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles 787system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles 788system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses 789system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses 790system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses 791system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses 792system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses 793system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses 794system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency 796system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency 798system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency 800system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states |
| 801system.cpu.l2cache.tags.replacements 0 # number of replacements | 801system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 802system.cpu.l2cache.tags.tagsinuse 231.224808 # Cycle average of tags in use 803system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. | 802system.cpu.l2cache.tags.tagsinuse 232.210591 # Cycle average of tags in use 803system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. |
| 804system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. | 804system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. |
| 805system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. | 805system.cpu.l2cache.tags.avg_refs 0.022573 # Average number of references to valid blocks. |
| 806system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 806system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 807system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.706281 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_blocks::cpu.data 63.518527 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.data 0.001938 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::total 0.007056 # Average percentage of cache occupancy | 807system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::total 0.007087 # Average percentage of cache occupancy |
| 812system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id | 812system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id |
| 813system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id | 813system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id |
| 815system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id | 815system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id |
| 816system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses 817system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses 818system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 819system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 820system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits | 816system.cpu.l2cache.tags.tag_accesses 4083 # Number of tag accesses 817system.cpu.l2cache.tags.data_accesses 4083 # Number of data accesses 818system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 819system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 820system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits |
| 821system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 822system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits | 821system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 822system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits |
| 823system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits | 823system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits |
| 824system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits | 824system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits |
| 825system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 826system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits | 825system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits 826system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits |
| 827system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits | 827system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits |
| 828system.cpu.l2cache.overall_hits::total 8 # number of overall hits | 828system.cpu.l2cache.overall_hits::total 10 # number of overall hits |
| 829system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses | 829system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses |
| 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 835system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses 840system.cpu.l2cache.overall_misses::total 446 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620000 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 4620000 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27705000 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 27705000 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4563000 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 4563000 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 27705000 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 9183000 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 36888000 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 27705000 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 9183000 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 36888000 # number of overall miss cycles | 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::total 56 # number of ReadSharedReq misses 835system.cpu.l2cache.demand_misses::cpu.inst 342 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 103 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 342 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 103 # number of overall misses 840system.cpu.l2cache.overall_misses::total 445 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620500 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 4620500 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27538000 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 27538000 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4709000 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 4709000 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 27538000 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 9329500 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 36867500 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 27538000 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 9329500 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 36867500 # number of overall miss cycles |
| 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) | 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) |
| 857system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 57 # number of ReadSharedReq accesses(hits+misses) 858system.cpu.l2cache.ReadSharedReq_accesses::total 57 # number of ReadSharedReq accesses(hits+misses) | 857system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) 858system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) |
| 859system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses | 859system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses |
| 860system.cpu.l2cache.demand_accesses::cpu.data 104 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses | 860system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::total 455 # number of demand (read+write) accesses |
| 862system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses | 862system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses |
| 863system.cpu.l2cache.overall_accesses::cpu.data 104 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses | 863system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::total 455 # number of overall (read+write) accesses |
| 865system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 865system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 867system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964912 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964912 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 0.980769 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.982379 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179 # average overall miss latency | 867system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98308.510638 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98308.510638 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80520.467836 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80520.467836 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84089.285714 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84089.285714 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 82848.314607 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency |
| 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 896system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses | 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 896system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses |
| 897system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 898system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 899system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 900system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 901system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 902system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 903system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 905system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 906system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 907system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150000 # number of ReadExReq MSHR miss cycles 908system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150000 # number of ReadExReq MSHR miss cycles 909system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24275000 # number of ReadCleanReq MSHR miss cycles 910system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24275000 # number of ReadCleanReq MSHR miss cycles 911system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4033000 # number of ReadSharedReq MSHR miss cycles 912system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4033000 # number of ReadSharedReq MSHR miss cycles 913system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24275000 # number of demand (read+write) MSHR miss cycles 914system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8183000 # number of demand (read+write) MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::total 32458000 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24275000 # number of overall MSHR miss cycles 917system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8183000 # number of overall MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::total 32458000 # number of overall MSHR miss cycles | 897system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses 898system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses 899system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 900system.cpu.l2cache.ReadSharedReq_mshr_misses::total 56 # number of ReadSharedReq MSHR misses 901system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses 902system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses 903system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses 905system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses 906system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 907system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles 908system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles 909system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles 910system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles 911system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles 912system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles 913system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles 914system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles 917system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles |
| 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 921system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 922system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 923system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses 924system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses 927system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses 930system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses 931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340 # average ReadExReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465 # average ReadCleanReq mshr miss latency 934system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465 # average ReadCleanReq mshr miss latency 935system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727 # average ReadSharedReq mshr miss latency 936system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727 # average ReadSharedReq mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency 943system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 944system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 921system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses 922system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses 923system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses 924system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses 927system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses 930system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses 931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency 934system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency 935system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency 936system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency 943system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. 944system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 945system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 946system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 947system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 948system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 945system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 946system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 947system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 948system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 949system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states 950system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution | 949system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 950system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution |
| 951system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution | 951system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution |
| 954system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution | 954system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution |
| 955system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) | 955system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) |
| 956system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) | 956system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) |
| 958system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) | 958system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) |
| 959system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) | 959system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) |
| 961system.cpu.toL2Bus.snoops 0 # Total snoops (count) 962system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 961system.cpu.toL2Bus.snoops 0 # Total snoops (count) 962system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 963system.cpu.toL2Bus.snoop_fanout::samples 454 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::mean 0.017621 # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::stdev 0.131715 # Request fanout histogram | 963system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram |
| 966system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 966system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 967system.cpu.toL2Bus.snoop_fanout::0 446 98.24% 98.24% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::1 8 1.76% 100.00% # Request fanout histogram | 967system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram |
| 969system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 969system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 973system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram 974system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) | 973system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram 974system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) |
| 975system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 976system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 977system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) | 975system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 976system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 977system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) |
| 978system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) | 978system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) |
| 979system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 979system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 980system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. | 980system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. |
| 981system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 982system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 983system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 984system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 985system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 981system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 982system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 983system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 984system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 985system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 986system.membus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states | 986system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states |
| 987system.membus.trans_dist::ReadResp 396 # Transaction distribution 988system.membus.trans_dist::ReadExReq 47 # Transaction distribution 989system.membus.trans_dist::ReadExResp 47 # Transaction distribution | 987system.membus.trans_dist::ReadResp 396 # Transaction distribution 988system.membus.trans_dist::ReadExReq 47 # Transaction distribution 989system.membus.trans_dist::ReadExResp 47 # Transaction distribution |
| 990system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution 991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 992system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) | 990system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution 991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) 992system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) |
| 993system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 995system.membus.snoops 0 # Total snoops (count) 996system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 993system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 995system.membus.snoops 0 # Total snoops (count) 996system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 997system.membus.snoop_fanout::samples 445 # Request fanout histogram | 997system.membus.snoop_fanout::samples 444 # Request fanout histogram |
| 998system.membus.snoop_fanout::mean 0 # Request fanout histogram 999system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1000system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 998system.membus.snoop_fanout::mean 0 # Request fanout histogram 999system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1000system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1001system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram | 1001system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram |
| 1002system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1005system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1002system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1005system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1006system.membus.snoop_fanout::total 445 # Request fanout histogram | 1006system.membus.snoop_fanout::total 444 # Request fanout histogram |
| 1007system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) 1008system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) | 1007system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) 1008system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) |
| 1009system.membus.respLayer1.occupancy 2325250 # Layer occupancy (ticks) 1010system.membus.respLayer1.utilization 10.9 # Layer utilization (%) | 1009system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) 1010system.membus.respLayer1.utilization 11.0 # Layer utilization (%) |
| 1011 1012---------- End Simulation Statistics ---------- | 1011 1012---------- End Simulation Statistics ---------- |