| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 19908000 # Number of ticks simulated 5final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 20159000 # Number of ticks simulated 5final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79311 # Simulator instruction rate (inst/s) 8host_op_rate 79299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 272523705 # Simulator tick rate (ticks/s) 10host_mem_usage 246096 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 70194 # Simulator instruction rate (inst/s) 8host_op_rate 70182 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 244226628 # Simulator tick rate (ticks/s) 10host_mem_usage 249960 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 443 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 443 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 445 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 445 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 19857500 # Total gap between requests | 79system.physmem.totGap 20108500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 445 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 445 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation |
| 192system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation | 192system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation |
| 197system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation |
| 203system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation | 202system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation |
| 204system.physmem.totQLat 3759500 # Total ticks spent queuing 205system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 3790750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 11.18 # Data bus utilization in percentage 216system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 11.04 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 360 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 360 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 44623.60 # Average gap between requests | 223system.physmem.avgGap 45187.64 # Average gap between requests |
| 225system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) | 224system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) | 227system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ) 234system.physmem_0.averagePower 949.326386 # Core power per rank (mW) | 230system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ) 233system.physmem_0.averagePower 947.872361 # Core power per rank (mW) |
| 235system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 236system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states |
| 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 245system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ) 248system.physmem_1.averagePower 748.316438 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states | 244system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ) 247system.physmem_1.averagePower 747.441023 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states |
| 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 253system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 255system.cpu.branchPred.lookups 2407 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 691 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_hits 0 # DTB write hits 282system.cpu.itb.write_misses 0 # DTB write misses 283system.cpu.itb.write_accesses 0 # DTB write accesses 284system.cpu.itb.hits 0 # DTB hits 285system.cpu.itb.misses 0 # DTB misses 286system.cpu.itb.accesses 0 # DTB accesses 287system.cpu.workload.num_syscalls 9 # Number of system calls | 254system.cpu.branchPred.lookups 2407 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 691 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 279system.cpu.itb.read_accesses 0 # DTB read accesses 280system.cpu.itb.write_hits 0 # DTB write hits 281system.cpu.itb.write_misses 0 # DTB write misses 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 9 # Number of system calls |
| 288system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states 289system.cpu.numCycles 39817 # number of cpu cycles simulated | 287system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states 288system.cpu.numCycles 40319 # number of cpu cycles simulated |
| 290system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 291system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 292system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss 293system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed | 291system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss 292system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed |
| 294system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered 295system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken | 293system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered 294system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken |
| 296system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked | 295system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked |
| 297system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing 298system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 299system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps 300system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR | 296system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing 297system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 298system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps 299system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR |
| 301system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched 302system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed 303system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched 301system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed 302system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total) |
| 306system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 307system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total) | 306system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total) |
| 316system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 319system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle 321system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle 322system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle 323system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked | 318system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle 320system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked |
| 324system.cpu.decode.RunCycles 1948 # Number of cycles decode is running 325system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking 326system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing 327system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch 328system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction | 323system.cpu.decode.RunCycles 1948 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing 326system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch 327system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction |
| 329system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode 330system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode | 328system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode 329system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode |
| 331system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing | 330system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing |
| 332system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle 333system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking 334system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst 335system.cpu.rename.RunCycles 1898 # Number of cycles rename is running 336system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking 337system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename | 331system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle 332system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking 333system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst 334system.cpu.rename.RunCycles 1896 # Number of cycles rename is running 335system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking 336system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename |
| 338system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 339system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full | 337system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 338system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full |
| 340system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full 341system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed 342system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made 343system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups | 339system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full 340system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed 341system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made 342system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups |
| 344system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 345system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed | 343system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 344system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed |
| 346system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing | 345system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing |
| 347system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 348system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 346system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 347system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 349system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer | 348system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer |
| 350system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit. | 349system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit. |
| 351system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit. | 350system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. |
| 352system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. 353system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. | 351system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. 352system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. |
| 354system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) | 353system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec) |
| 355system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ | 354system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ |
| 356system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued | 355system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued |
| 357system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued | 356system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued |
| 358system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling 359system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph | 357system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling 358system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph |
| 360system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed | 359system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed |
| 361system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle | 360system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle |
| 364system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 363system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 365system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle | 364system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 373system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 377system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle | 376system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle |
| 378system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available --- 22 unchanged lines hidden (view full) --- 408system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available 409system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 413system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued 414system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued 415system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued | 377system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available --- 22 unchanged lines hidden (view full) --- 407system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available 409system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 412system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued 413system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued 414system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued |
| 416system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued 442system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued | 415system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued 441system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued |
| 443system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 445system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 442system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued 443system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 446system.cpu.iq.FU_type_0::total 8811 # Type of FU issued 447system.cpu.iq.rate 0.221287 # Inst issue rate | 445system.cpu.iq.FU_type_0::total 8810 # Type of FU issued 446system.cpu.iq.rate 0.218507 # Inst issue rate |
| 448system.cpu.iq.fu_busy_cnt 189 # FU busy when requested | 447system.cpu.iq.fu_busy_cnt 189 # FU busy when requested |
| 449system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst) 450system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads 451system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes | 448system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst) 449system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads 450system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes |
| 452system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses 453system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 454system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 455system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses | 451system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses 452system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 453system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 454system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses |
| 456system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses | 455system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses |
| 457system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 458system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores 459system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 460system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed 461system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 462system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations | 456system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 457system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores 458system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 459system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed 460system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 461system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations |
| 463system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed | 462system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed |
| 464system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 465system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 466system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 467system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked 468system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 469system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing | 463system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 464system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 465system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 466system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked 467system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 468system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing |
| 470system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking | 469system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking |
| 471system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking | 470system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking |
| 472system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ | 471system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ |
| 473system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch 474system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions | 472system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch 473system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions |
| 475system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions | 474system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions |
| 476system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions 477system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 478system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall 479system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations 480system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 481system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly 482system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute 483system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions 484system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed | 475system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions 476system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 477system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall 478system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations 479system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 480system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly 481system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute 482system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions 483system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed |
| 485system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute | 484system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute |
| 486system.cpu.iew.exec_swp 0 # number of swp insts executed 487system.cpu.iew.exec_nop 0 # number of nop insts executed 488system.cpu.iew.exec_refs 3077 # number of memory reference insts executed | 485system.cpu.iew.exec_swp 0 # number of swp insts executed 486system.cpu.iew.exec_nop 0 # number of nop insts executed 487system.cpu.iew.exec_refs 3077 # number of memory reference insts executed |
| 489system.cpu.iew.exec_branches 1357 # Number of branches executed | 488system.cpu.iew.exec_branches 1359 # Number of branches executed |
| 490system.cpu.iew.exec_stores 1378 # Number of stores executed | 489system.cpu.iew.exec_stores 1378 # Number of stores executed |
| 491system.cpu.iew.exec_rate 0.212472 # Inst execution rate | 490system.cpu.iew.exec_rate 0.209827 # Inst execution rate |
| 492system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit 493system.cpu.iew.wb_count 8139 # cumulative count of insts written-back | 491system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit 492system.cpu.iew.wb_count 8139 # cumulative count of insts written-back |
| 494system.cpu.iew.wb_producers 4434 # num instructions producing a value 495system.cpu.iew.wb_consumers 7122 # num instructions consuming a value 496system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle 497system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back 498system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit | 493system.cpu.iew.wb_producers 4432 # num instructions producing a value 494system.cpu.iew.wb_consumers 7119 # num instructions consuming a value 495system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle 496system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back 497system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit |
| 499system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 500system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted | 498system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 499system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted |
| 501system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle |
| 504system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 503system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 505system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle | 504system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle |
| 514system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 517system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle | 516system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle |
| 518system.cpu.commit.committedInsts 5792 # Number of instructions committed 519system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 520system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 521system.cpu.commit.refs 2007 # Number of memory references committed 522system.cpu.commit.loads 961 # Number of loads committed 523system.cpu.commit.membars 7 # Number of memory barriers committed 524system.cpu.commit.branches 1037 # Number of branches committed 525system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 556system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 558system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 559system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 560system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 563system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached | 517system.cpu.commit.committedInsts 5792 # Number of instructions committed 518system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 519system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 520system.cpu.commit.refs 2007 # Number of memory references committed 521system.cpu.commit.loads 961 # Number of loads committed 522system.cpu.commit.membars 7 # Number of memory barriers committed 523system.cpu.commit.branches 1037 # Number of branches committed 524system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 555system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 557system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 558system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 559system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 560system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 562system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached |
| 564system.cpu.rob.rob_reads 21317 # The number of ROB reads 565system.cpu.rob.rob_writes 21174 # The number of ROB writes 566system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself 567system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling | 563system.cpu.rob.rob_reads 21857 # The number of ROB reads 564system.cpu.rob.rob_writes 21183 # The number of ROB writes 565system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 566system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 568system.cpu.committedInsts 5792 # Number of Instructions Simulated 569system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated | 567system.cpu.committedInsts 5792 # Number of Instructions Simulated 568system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated |
| 570system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction 571system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads 572system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle 573system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads 574system.cpu.int_regfile_reads 13370 # number of integer regfile reads 575system.cpu.int_regfile_writes 7150 # number of integer regfile writes | 569system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction 570system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads 571system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle 572system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads 573system.cpu.int_regfile_reads 13369 # number of integer regfile reads 574system.cpu.int_regfile_writes 7149 # number of integer regfile writes |
| 576system.cpu.fp_regfile_reads 25 # number of floating regfile reads 577system.cpu.fp_regfile_writes 2 # number of floating regfile writes | 575system.cpu.fp_regfile_reads 25 # number of floating regfile reads 576system.cpu.fp_regfile_writes 2 # number of floating regfile writes |
| 578system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 579system.cpu.dcache.tags.replacements 0 # number of replacements | 578system.cpu.dcache.tags.replacements 0 # number of replacements |
| 580system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use | 579system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use |
| 581system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. 582system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 583system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. 584system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 580system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 585system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor 586system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy | 584system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy |
| 588system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id | 587system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id |
| 589system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id | 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id |
| 591system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 592system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses 593system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses | 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses |
| 594system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 595system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 599system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits 600system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits 601system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits 602system.cpu.dcache.overall_hits::total 2199 # number of overall hits 603system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 604system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 605system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses 606system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses 607system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses 608system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses 609system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses 610system.cpu.dcache.overall_misses::total 437 # number of overall misses | 594system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 598system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits 599system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits 600system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits 601system.cpu.dcache.overall_hits::total 2199 # number of overall hits 602system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 603system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 604system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses 605system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses 606system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses 607system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses 608system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses 609system.cpu.dcache.overall_misses::total 437 # number of overall misses |
| 611system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles 612system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles 615system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles 616system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles 617system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles 618system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles | 610system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles 611system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles 612system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles 614system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles 615system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles 616system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles 617system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles |
| 619system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses 624system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses 625system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses 626system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses 627system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses 628system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses 629system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses 630system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses 631system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses 632system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses 633system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses 634system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses | 618system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses) 619system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses 623system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses 624system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses 625system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses 626system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses 627system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses 628system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses 629system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses 630system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses 631system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses 632system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses 633system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses |
| 635system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency 636system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency 639system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency 640system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency 643system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked | 634system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency 635system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency 636system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency 638system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency 639system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency 640system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency 642system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked |
| 644system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 643system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 647system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked | 646system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked |
| 648system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 650system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 651system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits 652system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits 653system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 654system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 655system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 656system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits 657system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses 658system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses 659system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 660system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 661system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses 662system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses 663system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses 664system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses | 647system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 649system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 650system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits 651system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits 652system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 653system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 654system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 655system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits 656system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses 657system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses 658system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 659system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 660system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses 661system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses 662system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses 663system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses |
| 665system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles 667system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles 668system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles 669system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles 670system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles 671system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles 672system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles | 664system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles 665system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles 666system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles 667system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles 668system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles 669system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles 670system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles 671system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles |
| 673system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 677system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for demand accesses 678system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses 679system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses 680system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses | 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for demand accesses 677system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses 678system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses 679system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses |
| 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency 685system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 686system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 687system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 688system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 689system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 680system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency 682system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency 684system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency 685system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency 686system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency 687system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency 688system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 690system.cpu.icache.tags.replacements 0 # number of replacements | 689system.cpu.icache.tags.replacements 0 # number of replacements |
| 691system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use 692system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. | 690system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use 691system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks. |
| 693system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. | 692system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. |
| 694system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. | 693system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks. |
| 695system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 694system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 696system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor 697system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy 698system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy | 695system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor 696system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy 697system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy |
| 699system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id | 698system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id |
| 700system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 701system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id | 699system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id |
| 702system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id | 701system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id |
| 703system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses 704system.cpu.icache.tags.data_accesses 4061 # Number of data accesses 705system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states 706system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits 707system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits 708system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits 709system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits 710system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits 711system.cpu.icache.overall_hits::total 1420 # number of overall hits | 702system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 4059 # Number of data accesses 704system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states 705system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits 710system.cpu.icache.overall_hits::total 1419 # number of overall hits |
| 712system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses 713system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses 714system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses 715system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses 716system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses 717system.cpu.icache.overall_misses::total 436 # number of overall misses | 711system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses 713system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses 714system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses 715system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses 716system.cpu.icache.overall_misses::total 436 # number of overall misses |
| 718system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles 719system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles 720system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles 721system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles 722system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles 723system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles 724system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses) 726system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses 727system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses 728system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses 729system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses 730system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses 731system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses 732system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses 733system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses 734system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses 735system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses 736system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency 737system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency 738system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency 739system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency 741system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency 742system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked | 717system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles 718system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles 719system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles 720system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles 721system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles 722system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles 723system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses 726system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses 727system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses 728system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses 729system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses 730system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses 731system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses 732system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses 733system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses 734system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses 735system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency 736system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency 737system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency 738system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency 741system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked |
| 743system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 744system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 745system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 742system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 744system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 746system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked | 745system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked |
| 747system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 748system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 749system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 750system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 751system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 752system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 753system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 754system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 755system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 756system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 757system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 758system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 759system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses | 746system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 748system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 749system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 750system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 751system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 752system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 753system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 754system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 755system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 756system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 757system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 758system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses |
| 760system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles 761system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles 762system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles 763system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles 764system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles 765system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles 766system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses 767system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses 768system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses 769system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses 770system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses 771system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 778system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 759system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles 760system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles 761system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles 762system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles 763system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles 764system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles 765system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses 766system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses 767system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses 768system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses 769system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses 770system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses 771system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency 773system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency 775system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency 777system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 779system.cpu.l2cache.tags.replacements 0 # number of replacements | 778system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 780system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use | 779system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use |
| 781system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. | 780system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. |
| 782system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 783system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. | 781system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. 782system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. |
| 784system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 783system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 785system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy 788system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id 791system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 792system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 793system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id | 784system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor 785system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy 787system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy 788system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id 790system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id 791system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 792system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id |
| 794system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses 795system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses | 793system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses 794system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses |
| 796system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 795system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 797system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 798system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 799system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 800system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 801system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits --- 6 unchanged lines hidden (view full) --- 811system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 812system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 813system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses 815system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 816system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 817system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses 818system.cpu.l2cache.overall_misses::total 446 # number of overall misses | 796system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 797system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 798system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 799system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 800system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 803system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits --- 6 unchanged lines hidden (view full) --- 810system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 811system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 812system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 813system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 815system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 816system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses 817system.cpu.l2cache.overall_misses::total 446 # number of overall misses |
| 819system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles 820system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles 822system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles 824system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles | 818system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles 819system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles 820system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles 822system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles 824system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles 827system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles |
| 831system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 833system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 834system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) 835system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 57 # number of ReadSharedReq accesses(hits+misses) 836system.cpu.l2cache.ReadSharedReq_accesses::total 57 # number of ReadSharedReq accesses(hits+misses) 837system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 838system.cpu.l2cache.demand_accesses::cpu.data 104 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 847system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964912 # miss rate for ReadSharedReq accesses 848system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964912 # miss rate for ReadSharedReq accesses 849system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::cpu.data 0.980769 # miss rate for demand accesses 851system.cpu.l2cache.demand_miss_rate::total 0.982379 # miss rate for demand accesses 852system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses 854system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses | 830system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 831system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 833system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) 834system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 57 # number of ReadSharedReq accesses(hits+misses) 835system.cpu.l2cache.ReadSharedReq_accesses::total 57 # number of ReadSharedReq accesses(hits+misses) 836system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 837system.cpu.l2cache.demand_accesses::cpu.data 104 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 846system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964912 # miss rate for ReadSharedReq accesses 847system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964912 # miss rate for ReadSharedReq accesses 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 849system.cpu.l2cache.demand_miss_rate::cpu.data 0.980769 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::total 0.982379 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 852system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses |
| 855system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency 856system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency 858system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency 860system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency 863system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency | 854system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency 855system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency 856system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency 858system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency |
| 867system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 872system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 875system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 876system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 877system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 878system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 883system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 884system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses | 866system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 875system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 876system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 877system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 883system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses |
| 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles 886system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles 888system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles 890system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles | 884system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles 886system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles 888system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles |
| 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses | 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses |
| 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency 910system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency 912system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency | 908system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency 910system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency 912system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency |
| 921system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 922system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 923system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 924system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 925system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 926system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 920system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 921system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 922system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 923system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 927system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 926system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 928system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution 933system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 950system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram 952system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) 953system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 954system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 955system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 956system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) 957system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 927system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution 932system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 933system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 949system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram 951system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) 952system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 953system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 954system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 955system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) 956system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 958system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states | 957system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 958system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 959system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 960system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 961system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 962system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 963system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states |
| 959system.membus.trans_dist::ReadResp 396 # Transaction distribution 960system.membus.trans_dist::ReadExReq 47 # Transaction distribution 961system.membus.trans_dist::ReadExResp 47 # Transaction distribution 962system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution 963system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 964system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 965system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 966system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 972system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 973system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram 974system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 975system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 976system.membus.snoop_fanout::min_value 0 # Request fanout histogram 977system.membus.snoop_fanout::max_value 0 # Request fanout histogram 978system.membus.snoop_fanout::total 445 # Request fanout histogram 979system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks) | 964system.membus.trans_dist::ReadResp 396 # Transaction distribution 965system.membus.trans_dist::ReadExReq 47 # Transaction distribution 966system.membus.trans_dist::ReadExResp 47 # Transaction distribution 967system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution 968system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 969system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 970system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 971system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 977system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 978system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram 979system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 980system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 981system.membus.snoop_fanout::min_value 0 # Request fanout histogram 982system.membus.snoop_fanout::max_value 0 # Request fanout histogram 983system.membus.snoop_fanout::total 445 # Request fanout histogram 984system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks) |
| 980system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 981system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks) 982system.membus.respLayer1.utilization 11.7 # Layer utilization (%) | 985system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 986system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks) 987system.membus.respLayer1.utilization 11.6 # Layer utilization (%) |
| 983 984---------- End Simulation Statistics ---------- | 988 989---------- End Simulation Statistics ---------- |