| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19908000 # Number of ticks simulated 5final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19908000 # Number of ticks simulated 5final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 120043 # Simulator instruction rate (inst/s) 8host_op_rate 120013 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 412413617 # Simulator tick rate (ticks/s) 10host_mem_usage 245176 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 67828 # Simulator instruction rate (inst/s) 8host_op_rate 67820 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 233087583 # Simulator tick rate (ticks/s) 10host_mem_usage 290888 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 443 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ) 247system.physmem_1.averagePower 748.316438 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 443 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ) 248system.physmem_1.averagePower 748.316438 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 2407 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 691 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 278system.cpu.itb.read_accesses 0 # DTB read accesses 279system.cpu.itb.write_hits 0 # DTB write hits 280system.cpu.itb.write_misses 0 # DTB write misses 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.hits 0 # DTB hits 283system.cpu.itb.misses 0 # DTB misses 284system.cpu.itb.accesses 0 # DTB accesses 285system.cpu.workload.num_syscalls 9 # Number of system calls | 255system.cpu.branchPred.lookups 2407 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 691 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_hits 0 # DTB write hits 282system.cpu.itb.write_misses 0 # DTB write misses 283system.cpu.itb.write_accesses 0 # DTB write accesses 284system.cpu.itb.hits 0 # DTB hits 285system.cpu.itb.misses 0 # DTB misses 286system.cpu.itb.accesses 0 # DTB accesses 287system.cpu.workload.num_syscalls 9 # Number of system calls |
| 288system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states |
|
| 286system.cpu.numCycles 39817 # number of cpu cycles simulated 287system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 288system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 289system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss 290system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed 291system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered 292system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken 293system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 567system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction 568system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads 569system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle 570system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads 571system.cpu.int_regfile_reads 13370 # number of integer regfile reads 572system.cpu.int_regfile_writes 7150 # number of integer regfile writes 573system.cpu.fp_regfile_reads 25 # number of floating regfile reads 574system.cpu.fp_regfile_writes 2 # number of floating regfile writes | 289system.cpu.numCycles 39817 # number of cpu cycles simulated 290system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 291system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 292system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss 293system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed 294system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered 295system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken 296system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 570system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction 571system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads 572system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle 573system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads 574system.cpu.int_regfile_reads 13370 # number of integer regfile reads 575system.cpu.int_regfile_writes 7150 # number of integer regfile writes 576system.cpu.fp_regfile_reads 25 # number of floating regfile reads 577system.cpu.fp_regfile_writes 2 # number of floating regfile writes |
| 578system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 575system.cpu.dcache.tags.replacements 0 # number of replacements 576system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use 577system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. 578system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 579system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. 580system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 581system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor 582system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy 583system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id 587system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 588system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses 589system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses | 579system.cpu.dcache.tags.replacements 0 # number of replacements 580system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use 581system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. 582system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 583system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. 584system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 585system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor 586system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy 588system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id 591system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 592system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses 593system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses |
| 594system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 590system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 591system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 592system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 593system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 594system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits 595system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits 596system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits 597system.cpu.dcache.overall_hits::total 2199 # number of overall hits --- 78 unchanged lines hidden (view full) --- 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency 680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency | 595system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 599system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits 600system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits 601system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits 602system.cpu.dcache.overall_hits::total 2199 # number of overall hits --- 78 unchanged lines hidden (view full) --- 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency 685system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 686system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 687system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 688system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency |
| 689system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 684system.cpu.icache.tags.replacements 0 # number of replacements 685system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use 686system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. 687system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 688system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. 689system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 690system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor 691system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy 692system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy 693system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 694system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 695system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 696system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 697system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses 698system.cpu.icache.tags.data_accesses 4061 # Number of data accesses | 690system.cpu.icache.tags.replacements 0 # number of replacements 691system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use 692system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. 693system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 694system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. 695system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 696system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor 697system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy 698system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy 699system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 701system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 702system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 703system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses 704system.cpu.icache.tags.data_accesses 4061 # Number of data accesses |
| 705system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 699system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits 700system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits 701system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits 702system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits 703system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits 704system.cpu.icache.overall_hits::total 1420 # number of overall hits 705system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses 706system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses 764system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency | 706system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits 707system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits 708system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits 709system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits 710system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits 711system.cpu.icache.overall_hits::total 1420 # number of overall hits 712system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses 713system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 770system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses 771system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency |
| 778system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 771system.cpu.l2cache.tags.replacements 0 # number of replacements 772system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use 773system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 774system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 775system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. 776system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 785system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id 786system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses 787system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses | 779system.cpu.l2cache.tags.replacements 0 # number of replacements 780system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use 781system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 782system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 783system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. 784system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 785system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy 788system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id 791system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 792system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 793system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id 794system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses 795system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses |
| 796system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
|
| 788system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 789system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 790system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 791system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 792system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 793system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 795system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits --- 114 unchanged lines hidden (view full) --- 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency 912system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 913system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 914system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 915system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 916system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 917system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 797system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 798system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 799system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 800system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 801system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits --- 114 unchanged lines hidden (view full) --- 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency 921system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 922system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 923system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 924system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 925system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 926system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 927system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
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| 918system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution 923system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 939system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram 941system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) 942system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 943system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 944system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 945system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) 946system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 928system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution 933system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 949system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram 951system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) 952system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 953system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 954system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 955system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) 956system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 957system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states |
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| 947system.membus.trans_dist::ReadResp 396 # Transaction distribution 948system.membus.trans_dist::ReadExReq 47 # Transaction distribution 949system.membus.trans_dist::ReadExResp 47 # Transaction distribution 950system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution 951system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 952system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 953system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 954system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 958system.membus.trans_dist::ReadResp 396 # Transaction distribution 959system.membus.trans_dist::ReadExReq 47 # Transaction distribution 960system.membus.trans_dist::ReadExResp 47 # Transaction distribution 961system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution 962system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 963system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 964system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) 965system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |