| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19908000 # Number of ticks simulated 5final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19908000 # Number of ticks simulated 5final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 56421 # Simulator instruction rate (inst/s) 8host_op_rate 56413 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 194020204 # Simulator tick rate (ticks/s) 10host_mem_usage 225060 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 130311 # Simulator instruction rate (inst/s) 8host_op_rate 130281 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 447700777 # Simulator tick rate (ticks/s) 10host_mem_usage 249300 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory --- 616 unchanged lines hidden (view full) --- 636system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency 637system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency 638system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked 639system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 641system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked 643system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory --- 616 unchanged lines hidden (view full) --- 636system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency 637system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency 638system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked 639system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 641system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked 643system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 644system.cpu.dcache.fast_writes 0 # number of fast writes performed 645system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 646system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 647system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits 649system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits 650system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 651system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 652system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 653system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency 679system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency 681system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 683system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 685system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency | 644system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 645system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 646system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits 648system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 649system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 650system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 651system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency 680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency |
| 686system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 687system.cpu.icache.tags.replacements 0 # number of replacements 688system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use 689system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. 690system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 691system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. 692system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 693system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor 694system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 736system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency 737system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency 738system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked 739system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 740system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 741system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 742system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked 743system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 684system.cpu.icache.tags.replacements 0 # number of replacements 685system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use 686system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. 687system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 688system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. 689system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 690system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor 691system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 733system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency 734system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency 735system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked 736system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 738system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked 740system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 744system.cpu.icache.fast_writes 0 # number of fast writes performed 745system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 746system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 747system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 748system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 749system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 750system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 751system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 752system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 753system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 768system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses 769system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses 770system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency 771system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency 772system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 773system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 774system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 775system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency | 741system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 742system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 743system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 744system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 745system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 746system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 747system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 748system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses 764system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency |
| 776system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 777system.cpu.l2cache.tags.replacements 0 # number of replacements 778system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use 779system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 780system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 781system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. 782system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 783system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 862system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency 864system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 865system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 866system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 869system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 771system.cpu.l2cache.tags.replacements 0 # number of replacements 772system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use 773system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 774system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. 775system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. 776system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 856system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency 857system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency 858system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 859system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 861system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 862system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 863system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 870system.cpu.l2cache.fast_writes 0 # number of fast writes performed 871system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 875system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 876system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 877system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 912system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency | 864system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 867system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 868system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 869system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 870system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 904system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency 905system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency 906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency 909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency |
| 920system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 921system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 922system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 923system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 924system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 925system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 926system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 927system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution --- 52 unchanged lines hidden --- | 912system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. 913system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 914system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 915system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 916system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 917system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 918system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution --- 52 unchanged lines hidden --- |