| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 19922000 # Number of ticks simulated 5final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 19923000 # Number of ticks simulated 5final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 38523 # Simulator instruction rate (inst/s) 8host_op_rate 38518 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 132470471 # Simulator tick rate (ticks/s) 10host_mem_usage 286104 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host | 7host_inst_rate 93968 # Simulator instruction rate (inst/s) 8host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 323084408 # Simulator tick rate (ticks/s) 10host_mem_usage 291680 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 19782500 # Total gap between requests | 78system.physmem.totGap 19783500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation |
| 203system.physmem.totQLat 3750750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 3746750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.14 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 359 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.14 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 359 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 44555.18 # Average gap between requests | 223system.physmem.avgGap 44557.43 # Average gap between requests |
| 224system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) --- 8 unchanged lines hidden (view full) --- 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) 247system.physmem_1.averagePower 748.283278 # Core power per rank (mW) | 224system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) --- 8 unchanged lines hidden (view full) --- 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) 247system.physmem_1.averagePower 748.283278 # Core power per rank (mW) |
| 248system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states | 248system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2359 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups --- 17 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2359 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups --- 17 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls |
| 282system.cpu.numCycles 39845 # number of cpu cycles simulated | 282system.cpu.numCycles 39847 # number of cpu cycles simulated |
| 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 305system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) | 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 305system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) |
| 313system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle | 313system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle |
| 315system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 1924 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing 320system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction 322system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode --- 109 unchanged lines hidden (view full) --- 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 8840 # Type of FU issued | 315system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 1924 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing 320system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction 322system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode --- 109 unchanged lines hidden (view full) --- 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 8840 # Type of FU issued |
| 440system.cpu.iq.rate 0.221860 # Inst issue rate | 440system.cpu.iq.rate 0.221849 # Inst issue rate |
| 441system.cpu.iq.fu_busy_cnt 201 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 476system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed 481system.cpu.iew.exec_refs 3121 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1355 # Number of branches executed 483system.cpu.iew.exec_stores 1414 # Number of stores executed | 441system.cpu.iq.fu_busy_cnt 201 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 476system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed 481system.cpu.iew.exec_refs 3121 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1355 # Number of branches executed 483system.cpu.iew.exec_stores 1414 # Number of stores executed |
| 484system.cpu.iew.exec_rate 0.212950 # Inst execution rate | 484system.cpu.iew.exec_rate 0.212939 # Inst execution rate |
| 485system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8147 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4452 # num instructions producing a value 488system.cpu.iew.wb_consumers 7114 # num instructions consuming a value 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 485system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8147 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4452 # num instructions producing a value 488system.cpu.iew.wb_consumers 7114 # num instructions consuming a value 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 490system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle | 490system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle |
| 491system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 493system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 558system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached 559system.cpu.rob.rob_reads 21420 # The number of ROB reads 560system.cpu.rob.rob_writes 21108 # The number of ROB writes 561system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself | 491system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 493system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 558system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached 559system.cpu.rob.rob_reads 21420 # The number of ROB reads 560system.cpu.rob.rob_writes 21108 # The number of ROB writes 561system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 562system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling | 562system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 563system.cpu.committedInsts 5792 # Number of Instructions Simulated 564system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated | 563system.cpu.committedInsts 5792 # Number of Instructions Simulated 564system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated |
| 565system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads 567system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads | 565system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads 567system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads |
| 569system.cpu.int_regfile_reads 13451 # number of integer regfile reads 570system.cpu.int_regfile_writes 7138 # number of integer regfile writes 571system.cpu.fp_regfile_reads 25 # number of floating regfile reads 572system.cpu.fp_regfile_writes 2 # number of floating regfile writes 573system.cpu.dcache.tags.replacements 0 # number of replacements | 569system.cpu.int_regfile_reads 13451 # number of integer regfile reads 570system.cpu.int_regfile_writes 7138 # number of integer regfile writes 571system.cpu.fp_regfile_reads 25 # number of floating regfile reads 572system.cpu.fp_regfile_writes 2 # number of floating regfile writes 573system.cpu.dcache.tags.replacements 0 # number of replacements |
| 574system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use | 574system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use |
| 575system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. 576system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. 577system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. 578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 575system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. 576system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. 577system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. 578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 579system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor | 579system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor |
| 580system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy 581system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 585system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id 586system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses 587system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 596system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses 597system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses 598system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses 599system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses 600system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses 601system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses 602system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses 603system.cpu.dcache.overall_misses::total 433 # number of overall misses | 580system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy 581system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 585system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id 586system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses 587system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 596system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses 597system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses 598system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses 599system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses 600system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses 601system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses 602system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses 603system.cpu.dcache.overall_misses::total 433 # number of overall misses |
| 604system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles 605system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles | 604system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles 605system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles |
| 606system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles | 606system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles |
| 608system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles 609system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles 610system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles 611system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles | 608system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles 609system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles 610system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles 611system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles |
| 612system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) 613system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 615system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses 617system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses 618system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses 619system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses 620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses 624system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses 625system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses 626system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses 627system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses | 612system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) 613system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 615system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses 617system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses 618system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses 619system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses 620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses 624system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses 625system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses 626system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses 627system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses |
| 628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency 629system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency | 628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency 629system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency |
| 630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency | 630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency |
| 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency | 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency |
| 636system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 653system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 656system.cpu.dcache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses 657system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses 658system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses 659system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses | 636system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 653system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 656system.cpu.dcache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses 657system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses 658system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses 659system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses |
| 660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles | 660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles |
| 662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles | 662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles |
| 664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles | 664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles |
| 668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses 669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for demand accesses 673system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses 674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses 675system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses | 668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses 669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for demand accesses 673system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses 674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses 675system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses |
| 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency | 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency |
| 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency | 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency |
| 680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency | 680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency |
| 684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.icache.tags.replacements 0 # number of replacements | 684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.icache.tags.replacements 0 # number of replacements |
| 686system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use | 686system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use |
| 687system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. 688system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 689system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. 690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 687system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. 688system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 689system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. 690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 691system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor | 691system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor |
| 692system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy 693system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 695system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 696system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 697system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 698system.cpu.icache.tags.tag_accesses 3993 # Number of tag accesses 699system.cpu.icache.tags.data_accesses 3993 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 704system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits 705system.cpu.icache.overall_hits::total 1389 # number of overall hits 706system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses 707system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses 708system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses 709system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses 710system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses 711system.cpu.icache.overall_misses::total 433 # number of overall misses | 692system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy 693system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 695system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 696system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 697system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 698system.cpu.icache.tags.tag_accesses 3993 # Number of tag accesses 699system.cpu.icache.tags.data_accesses 3993 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 704system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits 705system.cpu.icache.overall_hits::total 1389 # number of overall hits 706system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses 707system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses 708system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses 709system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses 710system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses 711system.cpu.icache.overall_misses::total 433 # number of overall misses |
| 712system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles 713system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles 714system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles 715system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles 716system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles 717system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles | 712system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles 713system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles 714system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles 715system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles 716system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles 717system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles |
| 718system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) 719system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses 721system.cpu.icache.demand_accesses::total 1822 # number of demand (read+write) accesses 722system.cpu.icache.overall_accesses::cpu.inst 1822 # number of overall (read+write) accesses 723system.cpu.icache.overall_accesses::total 1822 # number of overall (read+write) accesses 724system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.237651 # miss rate for ReadReq accesses 725system.cpu.icache.ReadReq_miss_rate::total 0.237651 # miss rate for ReadReq accesses 726system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 # miss rate for demand accesses 727system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses 728system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses 729system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses | 718system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) 719system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses 721system.cpu.icache.demand_accesses::total 1822 # number of demand (read+write) accesses 722system.cpu.icache.overall_accesses::cpu.inst 1822 # number of overall (read+write) accesses 723system.cpu.icache.overall_accesses::total 1822 # number of overall (read+write) accesses 724system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.237651 # miss rate for ReadReq accesses 725system.cpu.icache.ReadReq_miss_rate::total 0.237651 # miss rate for ReadReq accesses 726system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 # miss rate for demand accesses 727system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses 728system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses 729system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses |
| 730system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency 731system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency 732system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency 733system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency 734system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency | 730system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency 731system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency 732system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency 733system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency 734system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency |
| 736system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked 737system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 739system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked 741system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.icache.fast_writes 0 # number of fast writes performed 743system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits 749system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits 750system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 751system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 752system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 753system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 754system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 755system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses | 736system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked 737system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 739system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked 741system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.icache.fast_writes 0 # number of fast writes performed 743system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits 749system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits 750system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 751system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 752system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 753system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 754system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 755system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses |
| 756system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles 758system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles | 756system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles 758system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles |
| 762system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses 763system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses 764system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses 765system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses 766system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses 767system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses | 762system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses 763system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses 764system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses 765system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses 766system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses 767system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses |
| 768system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency 770system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency 772system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency | 768system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency 770system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency 772system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency |
| 774system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 775system.cpu.l2cache.tags.replacements 0 # number of replacements | 774system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 775system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 776system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use | 776system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use |
| 777system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 778system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 779system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. 780system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 777system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 778system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 779system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. 780system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 781system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor 782system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor | 781system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor 782system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor |
| 783system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id | 783system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id |
| 787system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id | 787system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id |
| 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses 792system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 793system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 794system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 795system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 796system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits --- 11 unchanged lines hidden (view full) --- 808system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 809system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 810system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 811system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 812system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 813system.cpu.l2cache.overall_misses::total 445 # number of overall misses 814system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles 815system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles | 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses 792system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 793system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 794system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 795system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 796system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits --- 11 unchanged lines hidden (view full) --- 808system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 809system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 810system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 811system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 812system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 813system.cpu.l2cache.overall_misses::total 445 # number of overall misses 814system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles 815system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles |
| 816system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles 817system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles | 816system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles 817system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles |
| 818system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles 819system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles | 818system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles 819system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles |
| 820system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles | 820system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles |
| 821system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles | 821system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles |
| 822system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles 823system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles | 822system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles 823system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles |
| 824system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles | 824system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles |
| 825system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles | 825system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles |
| 826system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 827system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 828system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 829system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) 830system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 831system.cpu.l2cache.ReadSharedReq_accesses::total 56 # number of ReadSharedReq accesses(hits+misses) 832system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 833system.cpu.l2cache.demand_accesses::cpu.data 103 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 844system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 845system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses 846system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses 847system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 848system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses 849system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses 850system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency 851system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency | 826system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 827system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 828system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 829system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) 830system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 831system.cpu.l2cache.ReadSharedReq_accesses::total 56 # number of ReadSharedReq accesses(hits+misses) 832system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 833system.cpu.l2cache.demand_accesses::cpu.data 103 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 844system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 845system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses 846system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses 847system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 848system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses 849system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses 850system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency 851system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency |
| 852system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency 853system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency | 852system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency 853system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency |
| 854system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency 855system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency | 854system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency 855system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency |
| 856system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency | 856system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency |
| 857system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency | 857system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency |
| 858system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency 859system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency | 858system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency 859system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency |
| 860system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency | 860system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency |
| 861system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency | 861system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency |
| 862system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 863system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 864system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 865system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 866system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 867system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 868system.cpu.l2cache.fast_writes 0 # number of fast writes performed 869system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 876system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 882system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles 883system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles | 862system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 863system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 864system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 865system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 866system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 867system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 868system.cpu.l2cache.fast_writes 0 # number of fast writes performed 869system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 876system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 882system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles 883system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles |
| 884system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles 885system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles | 884system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles 885system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles |
| 886system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles 887system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles | 886system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles 887system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles |
| 888system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles | 888system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles |
| 889system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles | 889system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles |
| 890system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles | 890system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles |
| 892system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles | 892system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles |
| 893system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles | 893system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles |
| 894system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 901system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses 902system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses 903system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses 906system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency 907system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency | 894system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 901system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses 902system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses 903system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses 906system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency 907system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency |
| 908system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency 909system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency | 908system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency 909system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency |
| 910system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency 911system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency | 910system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency 911system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency |
| 912system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency | 912system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency |
| 913system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency | 913system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency |
| 914system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency | 914system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency |
| 916system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency | 916system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency |
| 917system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency | 917system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency |
| 918system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 918system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 919system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter. 920system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 921system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 922system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 923system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 924system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 919system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution 924system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes) 929system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) 930system.cpu.toL2Bus.snoops 0 # Total snoops (count) 931system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram | 925system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution 930system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 931system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 932system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) 933system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) 936system.cpu.toL2Bus.snoops 0 # Total snoops (count) 937system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram |
| 932system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 938system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram |
| 934system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 940system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 935system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram | 941system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram |
| 937system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 943system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 939system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 945system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 940system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram 942system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 943system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 944system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 945system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 946system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks) 947system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- | 946system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram 948system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 949system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 950system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 951system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 952system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks) 953system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- |