| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 20101000 # Number of ticks simulated 5final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 103196 # Simulator instruction rate (inst/s) 8host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) --- 542 unchanged lines hidden (view full) --- 551system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 558system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 20101000 # Number of ticks simulated 5final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 103196 # Simulator instruction rate (inst/s) 8host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) --- 542 unchanged lines hidden (view full) --- 551system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 558system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached |
| 559system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 560system.cpu.rob.rob_reads 22278 # The number of ROB reads 561system.cpu.rob.rob_writes 21482 # The number of ROB writes 562system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling 564system.cpu.committedInsts 5792 # Number of Instructions Simulated 565system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 566system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads --- 395 unchanged lines hidden --- | 559system.cpu.rob.rob_reads 22278 # The number of ROB reads 560system.cpu.rob.rob_writes 21482 # The number of ROB writes 561system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling 563system.cpu.committedInsts 5792 # Number of Instructions Simulated 564system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 565system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads --- 395 unchanged lines hidden --- |