| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18857500 # Number of ticks simulated 5final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 20101000 # Number of ticks simulated 5final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 101158 # Simulator instruction rate (inst/s) 8host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 329193143 # Simulator tick rate (ticks/s) 10host_mem_usage 288984 # Number of bytes of host memory used | 7host_inst_rate 103196 # Simulator instruction rate (inst/s) 8host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 357968408 # Simulator tick rate (ticks/s) 10host_mem_usage 289136 # Number of bytes of host memory used |
| 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory | 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 18724000 # Total gap between requests | 78system.physmem.totGap 19960500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 203system.physmem.totQLat 3635500 # Total ticks spent queuing 204system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation 203system.physmem.totQLat 3861750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 11.77 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 11.04 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 356 # Number of row buffer hits during reads | 219system.physmem.readRowHits 357 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 42171.17 # Average gap between requests 224system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 44956.08 # Average gap between requests 224system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 230system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) 233system.physmem_0.averagePower 961.471341 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states | 230system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) 233system.physmem_0.averagePower 951.571203 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states |
| 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 244system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) 247system.physmem_1.averagePower 751.599242 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states | 244system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) 247system.physmem_1.averagePower 747.063003 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 2332 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted | 253system.cpu.branchPred.lookups 2330 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted |
| 255system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect | 255system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect |
| 256system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 661 # Number of BTB hits | 256system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 660 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage | 259system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage |
| 260system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses --- 6 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls | 260system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses --- 6 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls |
| 282system.cpu.numCycles 37716 # number of cpu cycles simulated | 282system.cpu.numCycles 40203 # number of cpu cycles simulated |
| 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 285system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing 291system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 292system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps | 285system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing 291system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 292system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps |
| 293system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR | 293system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR |
| 294system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) | 294system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 300system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) |
| 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 312system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked | 312system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked |
| 317system.cpu.decode.RunCycles 1951 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking | 317system.cpu.decode.RunCycles 1951 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking |
| 319system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing | 319system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing |
| 320system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction | 320system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction |
| 322system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode 323system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst | 322system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode 323system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst |
| 328system.cpu.rename.RunCycles 1916 # Number of cycles rename is running | 328system.cpu.rename.RunCycles 1916 # Number of cycles rename is running |
| 329system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename | 329system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename |
| 331system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 332system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full | 331system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 332system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full |
| 333system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 334system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups | 333system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full 334system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups |
| 337system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 338system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed | 337system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 338system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed |
| 339system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing | 339system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing |
| 340system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 340system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 342system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. | 342system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. |
| 345system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 346system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. | 345system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 346system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. |
| 347system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) | 347system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) |
| 348system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ | 348system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ |
| 349system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued 351system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph | 349system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued 351system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph |
| 353system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed | 353system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed |
| 354system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle | 354system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle | 358system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle |
| 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 370system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle |
| 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 372system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available | 372system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available |
| 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 406system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued | 406system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 439system.cpu.iq.FU_type_0::total 9108 # Type of FU issued 440system.cpu.iq.rate 0.241489 # Inst issue rate 441system.cpu.iq.fu_busy_cnt 251 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses | 439system.cpu.iq.FU_type_0::total 9105 # Type of FU issued 440system.cpu.iq.rate 0.226476 # Inst issue rate 441system.cpu.iq.fu_busy_cnt 252 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses |
| 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses | 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses |
| 449system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses | 449system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses |
| 450system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses | 450system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses |
| 451system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores | 451system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores |
| 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 453system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed | 453system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed |
| 454system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 455system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 454system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 455system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 456system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed | 456system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed |
| 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 462system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking 465system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ | 462system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking 465system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ |
| 466system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch | 466system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch |
| 467system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions | 467system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions |
| 469system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions | 469system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions |
| 470system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall | 470system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall |
| 472system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly | 472system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly |
| 474system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute | 474system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute |
| 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed | 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 481system.cpu.iew.exec_refs 3329 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1361 # Number of branches executed | 481system.cpu.iew.exec_refs 3330 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1363 # Number of branches executed |
| 483system.cpu.iew.exec_stores 1554 # Number of stores executed | 483system.cpu.iew.exec_stores 1554 # Number of stores executed |
| 484system.cpu.iew.exec_rate 0.230724 # Inst execution rate 485system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8300 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4483 # num instructions producing a value 488system.cpu.iew.wb_consumers 7102 # num instructions consuming a value | 484system.cpu.iew.exec_rate 0.216427 # Inst execution rate 485system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8298 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4465 # num instructions producing a value 488system.cpu.iew.wb_consumers 7078 # num instructions consuming a value |
| 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 490system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back | 490system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back |
| 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 493system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit | 493system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit |
| 494system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards | 494system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards |
| 495system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle | 495system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle |
| 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 512system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle | 512system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle |
| 513system.cpu.commit.committedInsts 5792 # Number of instructions committed 514system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 516system.cpu.commit.refs 2007 # Number of memory references committed 517system.cpu.commit.loads 961 # Number of loads committed 518system.cpu.commit.membars 7 # Number of memory barriers committed 519system.cpu.commit.branches 1037 # Number of branches committed 520system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 550system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction | 513system.cpu.commit.committedInsts 5792 # Number of instructions committed 514system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 516system.cpu.commit.refs 2007 # Number of memory references committed 517system.cpu.commit.loads 961 # Number of loads committed 518system.cpu.commit.membars 7 # Number of memory barriers committed 519system.cpu.commit.branches 1037 # Number of branches committed 520system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 550system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction |
| 558system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached | 558system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached |
| 559system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 559system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 560system.cpu.rob.rob_reads 21860 # The number of ROB reads 561system.cpu.rob.rob_writes 21470 # The number of ROB writes 562system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling | 560system.cpu.rob.rob_reads 22278 # The number of ROB reads 561system.cpu.rob.rob_writes 21482 # The number of ROB writes 562system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 564system.cpu.committedInsts 5792 # Number of Instructions Simulated 565system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated | 564system.cpu.committedInsts 5792 # Number of Instructions Simulated 565system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated |
| 566system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads 568system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle 569system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads 570system.cpu.int_regfile_reads 13744 # number of integer regfile reads 571system.cpu.int_regfile_writes 7176 # number of integer regfile writes | 566system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads 568system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle 569system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads 570system.cpu.int_regfile_reads 13740 # number of integer regfile reads 571system.cpu.int_regfile_writes 7173 # number of integer regfile writes |
| 572system.cpu.fp_regfile_reads 25 # number of floating regfile reads 573system.cpu.fp_regfile_writes 2 # number of floating regfile writes 574system.cpu.dcache.tags.replacements 0 # number of replacements | 572system.cpu.fp_regfile_reads 25 # number of floating regfile reads 573system.cpu.fp_regfile_writes 2 # number of floating regfile writes 574system.cpu.dcache.tags.replacements 0 # number of replacements |
| 575system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use 576system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. | 575system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use 576system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. |
| 577system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. | 577system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. |
| 578system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. | 578system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. |
| 579system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 579system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 580system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor 581system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy | 580system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor 581system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy |
| 583system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id | 583system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id |
| 584system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id | 584system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id |
| 586system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 587system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 588system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses | 586system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 587system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 588system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses |
| 589system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits 596system.cpu.dcache.overall_hits::total 2261 # number of overall hits 597system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 598system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 599system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 600system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 601system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses 602system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses 603system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses 604system.cpu.dcache.overall_misses::total 452 # number of overall misses 605system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles 606system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles 609system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles 610system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles 611system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles 612system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles | 589system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits 596system.cpu.dcache.overall_hits::total 2276 # number of overall hits 597system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses 598system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses 599system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses 600system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses 601system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses 602system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses 603system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses 604system.cpu.dcache.overall_misses::total 437 # number of overall misses 605system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles 606system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles 609system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles 610system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles 611system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles 612system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles |
| 613system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) 615system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 617system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 618system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 619system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 620system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses | 613system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) 615system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 617system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 618system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 619system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 620system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses |
| 621system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses 622system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses 623system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses 625system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses 626system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses 627system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses 628system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses 629system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency 630system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency 633system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 634system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked | 621system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses 622system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses 623system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses 625system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses 626system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses 627system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses 628system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses 629system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency 630system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency 633system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency 634system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked |
| 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked | 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked |
| 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.dcache.fast_writes 0 # number of fast writes performed 644system.cpu.dcache.cache_copies 0 # number of cache copies performed | 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.dcache.fast_writes 0 # number of fast writes performed 644system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits | 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits |
| 653system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 654system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 656system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 657system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 658system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 659system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 660system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses | 653system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 654system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 656system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 657system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 658system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 659system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 660system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses |
| 661system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles 668system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles | 661system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles 668system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles |
| 669system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 673system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses 674system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses 675system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses 676system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses | 669system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 673system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses 674system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses 675system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses 676system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses |
| 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency | 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency |
| 685system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 686system.cpu.icache.tags.replacements 0 # number of replacements | 685system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 686system.cpu.icache.tags.replacements 0 # number of replacements |
| 687system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. | 687system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. |
| 689system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. | 689system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. |
| 690system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. | 690system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. |
| 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 692system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy | 692system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy |
| 695system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id | 695system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id |
| 696system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id | 696system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id |
| 698system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id | 698system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id |
| 699system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses 700system.cpu.icache.tags.data_accesses 4007 # Number of data accesses 701system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits 706system.cpu.icache.overall_hits::total 1391 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 712system.cpu.icache.overall_misses::total 438 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency 737system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked | 699system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses 700system.cpu.icache.tags.data_accesses 4005 # Number of data accesses 701system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits 706system.cpu.icache.overall_hits::total 1389 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses 712system.cpu.icache.overall_misses::total 439 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency 737system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked |
| 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 741system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked | 741system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked |
| 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed | 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 745system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 746system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 747system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 748system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 749system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 750system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits | 745system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits 746system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits 747system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits 748system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits 749system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits 750system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits |
| 751system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 752system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 753system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 754system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 755system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 756system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses | 751system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 752system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 753system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 754system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 755system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 756system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses |
| 757system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles 758system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles 762system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles 763system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses 764system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses 765system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses 766system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses 767system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses 768system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency 770system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 772system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 774system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency | 757system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles 758system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles 762system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles 763system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses 764system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses 765system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses 766system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses 767system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses 768system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency 770system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency 772system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency 774system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency |
| 775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.cpu.l2cache.tags.replacements 0 # number of replacements | 775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 777system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use | 777system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use |
| 778system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 778system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy | 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy |
| 787system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id | 787system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id |
| 788system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id | 788system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id |
| 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 796system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 797system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 805system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 806system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 807system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 808system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 809system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 810system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 811system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 812system.cpu.l2cache.overall_misses::total 445 # number of overall misses | 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 796system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 797system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 805system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 806system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 807system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 808system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 809system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 810system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 811system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 812system.cpu.l2cache.overall_misses::total 445 # number of overall misses |
| 813system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles 814system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles 815system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles 816system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles 817system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles | 813system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles 814system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles 815system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles 816system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles 817system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles |
| 824system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) 825system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 826system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 827system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 828system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 829system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 830system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 831system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 838system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 839system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 840system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 841system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 842system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses 843system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 844system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 845system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses | 824system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) 825system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 826system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 827system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 828system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 829system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 830system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 831system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 838system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 839system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 840system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 841system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 842system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses 843system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 844system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 845system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses |
| 846system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency 847system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency 848system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency 849system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency 850system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency 851system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 852system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 853system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency 854system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 855system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 856system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency | 846system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency 847system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency 848system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency 849system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency 850system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency 851system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency 852system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency 853system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency 854system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency 855system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency 856system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency |
| 857system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 858system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 859system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 861system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 862system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 863system.cpu.l2cache.fast_writes 0 # number of fast writes performed 864system.cpu.l2cache.cache_copies 0 # number of cache copies performed 865system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 866system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 867system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses 868system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 869system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 870system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 873system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 874system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 875system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses | 857system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 858system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 859system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 861system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 862system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 863system.cpu.l2cache.fast_writes 0 # number of fast writes performed 864system.cpu.l2cache.cache_copies 0 # number of cache copies performed 865system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 866system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 867system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses 868system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 869system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 870system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 873system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 874system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 875system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses |
| 876system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles 877system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles 879system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles 880system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles 881system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles 882system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles 883system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles 884system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles 885system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles 886system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles | 876system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles 877system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles 879system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles 880system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles 881system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles 882system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles 883system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles 884system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles 885system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles 886system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles |
| 887system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses 890system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 891system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 892system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 893system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 894system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses 895system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 896system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 897system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses | 887system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses 890system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 891system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 892system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 893system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 894system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses 895system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 896system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 897system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses |
| 898system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency 899system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency 900system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency 901system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency 902system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 904system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 905system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 907system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 908system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency | 898system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency 899system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency 900system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency 901system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency 902system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency 904system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency 905system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency 907system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency 908system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency |
| 909system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 910system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 914system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 915system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 916system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 925system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram 932system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) | 909system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 910system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 914system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 915system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 916system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 925system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram 932system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) |
| 933system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 934system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) 935system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) 936system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) 937system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 933system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 934system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) 935system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 936system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) 937system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 938system.membus.trans_dist::ReadReq 397 # Transaction distribution 939system.membus.trans_dist::ReadResp 397 # Transaction distribution 940system.membus.trans_dist::ReadExReq 47 # Transaction distribution 941system.membus.trans_dist::ReadExResp 47 # Transaction distribution 942system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 943system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 944system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 945system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 946system.membus.snoops 0 # Total snoops (count) 947system.membus.snoop_fanout::samples 444 # Request fanout histogram 948system.membus.snoop_fanout::mean 0 # Request fanout histogram 949system.membus.snoop_fanout::stdev 0 # Request fanout histogram 950system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 951system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram 952system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 953system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 954system.membus.snoop_fanout::min_value 0 # Request fanout histogram 955system.membus.snoop_fanout::max_value 0 # Request fanout histogram 956system.membus.snoop_fanout::total 444 # Request fanout histogram | 938system.membus.trans_dist::ReadReq 397 # Transaction distribution 939system.membus.trans_dist::ReadResp 397 # Transaction distribution 940system.membus.trans_dist::ReadExReq 47 # Transaction distribution 941system.membus.trans_dist::ReadExResp 47 # Transaction distribution 942system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 943system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 944system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 945system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 946system.membus.snoops 0 # Total snoops (count) 947system.membus.snoop_fanout::samples 444 # Request fanout histogram 948system.membus.snoop_fanout::mean 0 # Request fanout histogram 949system.membus.snoop_fanout::stdev 0 # Request fanout histogram 950system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 951system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram 952system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 953system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 954system.membus.snoop_fanout::min_value 0 # Request fanout histogram 955system.membus.snoop_fanout::max_value 0 # Request fanout histogram 956system.membus.snoop_fanout::total 444 # Request fanout histogram |
| 957system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) 958system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 959system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) 960system.membus.respLayer1.utilization 22.1 # Layer utilization (%) | 957system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) 958system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 959system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) 960system.membus.respLayer1.utilization 11.6 # Layer utilization (%) |
| 961 962---------- End Simulation Statistics ---------- | 961 962---------- End Simulation Statistics ---------- |