| stats.txt (10229:aae7735450a9) | stats.txt (10242:cb4e86c17767) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 19030500 # Number of ticks simulated 5final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 19030500 # Number of ticks simulated 5final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79159 # Simulator instruction rate (inst/s) 8host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 259986612 # Simulator tick rate (ticks/s) 10host_mem_usage 262500 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 17395 # Simulator instruction rate (inst/s) 8host_op_rate 17394 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57147442 # Simulator tick rate (ticks/s) 10host_mem_usage 218304 # Number of bytes of host memory used 11host_seconds 0.33 # Real time elapsed on the host |
| 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory --- 65 unchanged lines hidden (view full) --- 85system.physmem.readPktSize::6 446 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory --- 65 unchanged lines hidden (view full) --- 85system.physmem.readPktSize::6 446 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 80 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation | 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 80 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation |
| 195system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation | 195system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation |
| 202system.physmem.totQLat 3599250 # Total ticks spent queuing 203system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM | 202system.physmem.totQLat 3354000 # Total ticks spent queuing 203system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers | 204system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers |
| 205system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst | 205system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst | 207system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst |
| 208system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 11.72 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 208system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 11.72 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 216system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing | 216system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing |
| 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 358 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 42381.17 # Average gap between requests 223system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states --- 7 unchanged lines hidden (view full) --- 232system.membus.trans_dist::ReadExReq 47 # Transaction distribution 233system.membus.trans_dist::ReadExResp 47 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 28544 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 358 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 42381.17 # Average gap between requests 223system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states --- 7 unchanged lines hidden (view full) --- 232system.membus.trans_dist::ReadExReq 47 # Transaction distribution 233system.membus.trans_dist::ReadExResp 47 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 28544 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 240system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 242system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) | 240system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 242system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) |
| 243system.membus.respLayer1.utilization 22.0 # Layer utilization (%) 244system.cpu_clk_domain.clock 500 # Clock period in ticks | 243system.membus.respLayer1.utilization 22.0 # Layer utilization (%) 244system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 245system.cpu.branchPred.lookups 2235 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted | 245system.cpu.branchPred.lookups 2252 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted |
| 247system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect | 247system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect |
| 248system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 602 # Number of BTB hits | 248system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 610 # Number of BTB hits |
| 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 251system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage 252system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. | 251system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage 252system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. |
| 253system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. 254system.cpu.dtb.read_hits 0 # DTB read hits 255system.cpu.dtb.read_misses 0 # DTB read misses 256system.cpu.dtb.read_accesses 0 # DTB read accesses 257system.cpu.dtb.write_hits 0 # DTB write hits 258system.cpu.dtb.write_misses 0 # DTB write misses 259system.cpu.dtb.write_accesses 0 # DTB write accesses 260system.cpu.dtb.hits 0 # DTB hits --- 7 unchanged lines hidden (view full) --- 268system.cpu.itb.write_accesses 0 # DTB write accesses 269system.cpu.itb.hits 0 # DTB hits 270system.cpu.itb.misses 0 # DTB misses 271system.cpu.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 9 # Number of system calls 273system.cpu.numCycles 38062 # number of cpu cycles simulated 274system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 275system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 253system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. 254system.cpu.dtb.read_hits 0 # DTB read hits 255system.cpu.dtb.read_misses 0 # DTB read misses 256system.cpu.dtb.read_accesses 0 # DTB read accesses 257system.cpu.dtb.write_hits 0 # DTB write hits 258system.cpu.dtb.write_misses 0 # DTB write misses 259system.cpu.dtb.write_accesses 0 # DTB write accesses 260system.cpu.dtb.hits 0 # DTB hits --- 7 unchanged lines hidden (view full) --- 268system.cpu.itb.write_accesses 0 # DTB write accesses 269system.cpu.itb.hits 0 # DTB hits 270system.cpu.itb.misses 0 # DTB misses 271system.cpu.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 9 # Number of system calls 273system.cpu.numCycles 38062 # number of cpu cycles simulated 274system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 275system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 276system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss 277system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed 278system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered 279system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken 280system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked 281system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing 282system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked 283system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed 285system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) | 276system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss 277system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed 278system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered 279system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken 280system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked 281system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing 282system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked 283system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed 285system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total) |
| 288system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 288system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 289system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) | 289system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 298system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 301system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle 303system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle 304system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle 305system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked 306system.cpu.decode.RunCycles 2089 # Number of cycles decode is running 307system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking 308system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing 309system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch | 301system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle 303system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle 304system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle 305system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked 306system.cpu.decode.RunCycles 2174 # Number of cycles decode is running 307system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking 308system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing 309system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch |
| 310system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction | 310system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction |
| 311system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode 312system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode 313system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing 314system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle 315system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking 316system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst 317system.cpu.rename.RunCycles 1980 # Number of cycles rename is running 318system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking 319system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename | 311system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode 312system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode 313system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing 314system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle 315system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking 316system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst 317system.cpu.rename.RunCycles 2016 # Number of cycles rename is running 318system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking 319system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename |
| 320system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full | 320system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full |
| 321system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full 322system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed 323system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made 324system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups | 321system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full 322system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full 323system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed 324system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made 325system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups |
| 325system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 326system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed | 326system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 327system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed |
| 327system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing | 328system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing |
| 328system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 329system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 329system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 330system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 330system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer 331system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. 332system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 333system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. | 331system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer 332system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit. 333system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit. 334system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. |
| 334system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. | 335system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. |
| 335system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) | 336system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec) |
| 336system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ | 337system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ |
| 337system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued | 338system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued |
| 338system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued | 339system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued |
| 339system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling 340system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph | 340system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling 341system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph |
| 341system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed | 342system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed |
| 342system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle | 343system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle |
| 345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 346system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 346system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle | 347system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle |
| 355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 356system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle | 359system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle |
| 359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 360system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 360system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available 389system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available 390system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available | 361system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available 363system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 390system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available 391system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available |
| 391system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 392system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 393system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 392system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 393system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 394system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 394system.cpu.iq.FU_type_0::IntAlu 5476 61.52% 61.52% # Type of FU issued 395system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued 396system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued 423system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued 424system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued | 395system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued 396system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued 397system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued 424system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued 425system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued |
| 425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 426system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 427system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 427system.cpu.iq.FU_type_0::total 8901 # Type of FU issued 428system.cpu.iq.rate 0.233855 # Inst issue rate 429system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 430system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) 431system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads 432system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes 433system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses | 428system.cpu.iq.FU_type_0::total 8929 # Type of FU issued 429system.cpu.iq.rate 0.234591 # Inst issue rate 430system.cpu.iq.fu_busy_cnt 177 # FU busy when requested 431system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst) 432system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads 433system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes 434system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses |
| 434system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 435system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 436system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses | 435system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 436system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 437system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses |
| 437system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses | 438system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses |
| 438system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses | 439system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses |
| 439system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores | 440system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores |
| 440system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 441system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 441system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed | 442system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed |
| 442system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 443system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 443system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 444system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 444system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed | 445system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed |
| 445system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 446system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 447system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 448system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked 449system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 446system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 447system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 448system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 449system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked 450system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 450system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing 451system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking 452system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking 453system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ 454system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch 455system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions 456system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions | 451system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing 452system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking 453system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking 454system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ 455system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch 456system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions 457system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions |
| 457system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions 458system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall | 458system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions 459system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall |
| 459system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall | 460system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall |
| 460system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 461system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly 462system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 463system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute | 461system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 462system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly 463system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 464system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute |
| 464system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions 465system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed 466system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute | 465system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions 466system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed 467system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute |
| 467system.cpu.iew.exec_swp 0 # number of swp insts executed 468system.cpu.iew.exec_nop 0 # number of nop insts executed | 468system.cpu.iew.exec_swp 0 # number of swp insts executed 469system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 469system.cpu.iew.exec_refs 3201 # number of memory reference insts executed 470system.cpu.iew.exec_branches 1350 # Number of branches executed 471system.cpu.iew.exec_stores 1523 # Number of stores executed 472system.cpu.iew.exec_rate 0.223320 # Inst execution rate 473system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit 474system.cpu.iew.wb_count 8155 # cumulative count of insts written-back 475system.cpu.iew.wb_producers 4187 # num instructions producing a value 476system.cpu.iew.wb_consumers 6623 # num instructions consuming a value | 470system.cpu.iew.exec_refs 3211 # number of memory reference insts executed 471system.cpu.iew.exec_branches 1353 # Number of branches executed 472system.cpu.iew.exec_stores 1529 # Number of stores executed 473system.cpu.iew.exec_rate 0.224003 # Inst execution rate 474system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit 475system.cpu.iew.wb_count 8178 # cumulative count of insts written-back 476system.cpu.iew.wb_producers 4388 # num instructions producing a value 477system.cpu.iew.wb_consumers 6958 # num instructions consuming a value |
| 477system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 478system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 478system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle 479system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back | 479system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle 480system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back |
| 480system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 481system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 481system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit | 482system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit |
| 482system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 483system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted | 483system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 484system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted |
| 484system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle | 485system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle |
| 487system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 488system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 488system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle | 489system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle |
| 497system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 498system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle | 501system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle |
| 501system.cpu.commit.committedInsts 5792 # Number of instructions committed 502system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 503system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 504system.cpu.commit.refs 2007 # Number of memory references committed 505system.cpu.commit.loads 961 # Number of loads committed 506system.cpu.commit.membars 7 # Number of memory barriers committed 507system.cpu.commit.branches 1037 # Number of branches committed 508system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 538system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 542system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 543system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 544system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 545system.cpu.commit.op_class_0::total 5792 # Class of committed instruction | 502system.cpu.commit.committedInsts 5792 # Number of instructions committed 503system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 504system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 505system.cpu.commit.refs 2007 # Number of memory references committed 506system.cpu.commit.loads 961 # Number of loads committed 507system.cpu.commit.membars 7 # Number of memory barriers committed 508system.cpu.commit.branches 1037 # Number of branches committed 509system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 539system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 542system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 543system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 544system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 545system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 546system.cpu.commit.op_class_0::total 5792 # Class of committed instruction |
| 546system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached | 547system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached |
| 547system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 548system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 548system.cpu.rob.rob_reads 21428 # The number of ROB reads 549system.cpu.rob.rob_writes 21442 # The number of ROB writes 550system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself 551system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling | 549system.cpu.rob.rob_reads 21067 # The number of ROB reads 550system.cpu.rob.rob_writes 21539 # The number of ROB writes 551system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself 552system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 552system.cpu.committedInsts 5792 # Number of Instructions Simulated 553system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 554system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction 555system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads 556system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle 557system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads | 553system.cpu.committedInsts 5792 # Number of Instructions Simulated 554system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 555system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction 556system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads 557system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle 558system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads |
| 558system.cpu.int_regfile_reads 13470 # number of integer regfile reads 559system.cpu.int_regfile_writes 7047 # number of integer regfile writes | 559system.cpu.int_regfile_reads 13502 # number of integer regfile reads 560system.cpu.int_regfile_writes 7065 # number of integer regfile writes |
| 560system.cpu.fp_regfile_reads 25 # number of floating regfile reads 561system.cpu.fp_regfile_writes 2 # number of floating regfile writes 562system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) 563system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 567system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) 568system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) 571system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 572system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) 574system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 575system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 576system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 561system.cpu.fp_regfile_reads 25 # number of floating regfile reads 562system.cpu.fp_regfile_writes 2 # number of floating regfile writes 563system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) 564system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 568system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) 572system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) 575system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 576system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 577system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 577system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) | 578system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks) |
| 578system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) | 579system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) |
| 579system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) | 580system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks) |
| 580system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 581system.cpu.icache.tags.replacements 0 # number of replacements | 581system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 582system.cpu.icache.tags.replacements 0 # number of replacements |
| 582system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use 583system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. | 583system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use 584system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks. |
| 584system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. | 585system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. |
| 585system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. | 586system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks. |
| 586system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 587system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 587system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor 588system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy 589system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy | 588system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor 589system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy 590system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy |
| 590system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id | 591system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 593system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 594system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id |
| 594system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 3971 # Number of data accesses 596system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits 597system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits 598system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits 599system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits 600system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits 601system.cpu.icache.overall_hits::total 1369 # number of overall hits 602system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses 603system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses 604system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses 605system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses 606system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses 607system.cpu.icache.overall_misses::total 441 # number of overall misses 608system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles 609system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles 610system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles 611system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles 612system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles 613system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles 614system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) 615system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses 617system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses 618system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses 619system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses 620system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses 621system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses 622system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses 623system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses 624system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses 625system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses 626system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency 627system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency 628system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency 629system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency 630system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency | 595system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses 596system.cpu.icache.tags.data_accesses 3997 # Number of data accesses 597system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits 602system.cpu.icache.overall_hits::total 1380 # number of overall hits 603system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses 608system.cpu.icache.overall_misses::total 443 # number of overall misses 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency |
| 632system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked 633system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 635system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 636system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked 637system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 638system.cpu.icache.fast_writes 0 # number of fast writes performed 639system.cpu.icache.cache_copies 0 # number of cache copies performed | 633system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.fast_writes 0 # number of fast writes performed 640system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 640system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 641system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 642system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 643system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 644system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 645system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits | 641system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits 642system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits 643system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits 644system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 645system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 646system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits |
| 646system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 647system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 648system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 649system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 650system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 651system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses | 647system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 648system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 649system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 650system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 651system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 652system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses |
| 652system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles 653system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles 654system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses 659system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses 660system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses 661system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses 662system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses 663system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses 664system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency 666system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency 668system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency | 653system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles 654system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles 658system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses 661system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses 662system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses 663system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses 664system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency 666system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency 668system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency |
| 670system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 671system.cpu.l2cache.tags.replacements 0 # number of replacements | 671system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 672system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 672system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use | 673system.cpu.l2cache.tags.tagsinuse 199.437860 # Cycle average of tags in use |
| 673system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 674system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 675system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. 676system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 674system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 675system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 676system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. 677system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 677system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor 678system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy | 678system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.936913 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_blocks::cpu.data 31.500947 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005125 # Average percentage of cache occupancy |
| 680system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy | 681system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy |
| 681system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy | 682system.cpu.l2cache.tags.occ_percent::total 0.006086 # Average percentage of cache occupancy |
| 682system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id | 683system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id |
| 683system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id | 684system.cpu.l2cache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id |
| 685system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 686system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses 687system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses 688system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 689system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 690system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 691system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 692system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 700system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 701system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 702system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 703system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 705system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 706system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 707system.cpu.l2cache.overall_misses::total 446 # number of overall misses | 686system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 687system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses 688system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses 689system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 690system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 691system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 692system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 693system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 701system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 702system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 703system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 705system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 706system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 707system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 708system.cpu.l2cache.overall_misses::total 446 # number of overall misses |
| 708system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles 709system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles 710system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles 712system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles 713system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles 716system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles | 709system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23687250 # number of ReadReq miss cycles 710system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4073750 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadReq_miss_latency::total 27761000 # number of ReadReq miss cycles 712system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627250 # number of ReadExReq miss cycles 713system.cpu.l2cache.ReadExReq_miss_latency::total 3627250 # number of ReadExReq miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.inst 23687250 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::cpu.data 7701000 # number of demand (read+write) miss cycles 716system.cpu.l2cache.demand_miss_latency::total 31388250 # number of demand (read+write) miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.inst 23687250 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.data 7701000 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::total 31388250 # number of overall miss cycles |
| 719system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 720system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 725system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 726system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 733system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 734system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 735system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 736system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 738system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 739system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 740system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses | 720system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 725system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 726system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 727system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 736system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 739system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 740system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 741system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses |
| 741system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency 742system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency 743system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency 744system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency 745system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency 746system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency 747system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency 748system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency 750system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency | 742system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652 # average ReadReq miss latency 743system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815 # average ReadReq miss latency 744system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103 # average ReadReq miss latency 745system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915 # average ReadExReq miss latency 746system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915 # average ReadExReq miss latency 747system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency 748system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency 749system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152 # average overall miss latency 750system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency 752system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152 # average overall miss latency |
| 752system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 755system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 756system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 757system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 758system.cpu.l2cache.fast_writes 0 # number of fast writes performed 759system.cpu.l2cache.cache_copies 0 # number of cache copies performed 760system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses 761system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 762system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 763system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 764system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses | 753system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.l2cache.fast_writes 0 # number of fast writes performed 760system.cpu.l2cache.cache_copies 0 # number of cache copies performed 761system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses 762system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 763system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 764system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 765system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 771system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses |
| 771system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles | 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19339750 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3409250 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22749000 # number of ReadReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3052750 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3052750 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19339750 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6462000 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::total 25801750 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19339750 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6462000 # number of overall MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::total 25801750 # number of overall MSHR miss cycles |
| 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses | 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses |
| 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency | 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56057.246377 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63134.259259 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57015.037594 # average ReadReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64952.127660 # average ReadExReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64952.127660 # average ReadExReq mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency |
| 804system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu.dcache.tags.replacements 0 # number of replacements | 805system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.dcache.tags.replacements 0 # number of replacements |
| 806system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use 807system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. | 807system.cpu.dcache.tags.tagsinuse 63.722947 # Cycle average of tags in use 808system.cpu.dcache.tags.total_refs 2180 # Total number of references to valid blocks. |
| 808system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. | 809system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. |
| 809system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. | 810system.cpu.dcache.tags.avg_refs 21.372549 # Average number of references to valid blocks. |
| 810system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 811system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 811system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor 812system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy 813system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy | 812system.cpu.dcache.tags.occ_blocks::cpu.data 63.722947 # Average occupied blocks per requestor 813system.cpu.dcache.tags.occ_percent::cpu.data 0.015557 # Average percentage of cache occupancy 814system.cpu.dcache.tags.occ_percent::total 0.015557 # Average percentage of cache occupancy |
| 814system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 815system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 816system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 817system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id | 815system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 816system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 817system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 818system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id |
| 818system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses 819system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses 820system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits 821system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits | 819system.cpu.dcache.tags.tag_accesses 5332 # Number of tag accesses 820system.cpu.dcache.tags.data_accesses 5332 # Number of data accesses 821system.cpu.dcache.ReadReq_hits::cpu.data 1465 # number of ReadReq hits 822system.cpu.dcache.ReadReq_hits::total 1465 # number of ReadReq hits |
| 822system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits 823system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits | 823system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits 824system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits |
| 824system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits 825system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits 826system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits 827system.cpu.dcache.overall_hits::total 2188 # number of overall hits | 825system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits 826system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits 827system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits 828system.cpu.dcache.overall_hits::total 2180 # number of overall hits |
| 828system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 829system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses 830system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses 831system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses 832system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses 833system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses 834system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses 835system.cpu.dcache.overall_misses::total 435 # number of overall misses | 829system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 830system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses 831system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses 832system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses 833system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses 834system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses 835system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses 836system.cpu.dcache.overall_misses::total 435 # number of overall misses |
| 836system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles 837system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles 838system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles 839system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles 840system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles 841system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles 842system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles 843system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles 844system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) 845system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) | 837system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles 838system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles 839system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles 840system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles 841system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles 845system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) |
| 846system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) | 847system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) |
| 848system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses | 849system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses 850system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses 851system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses 852system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses 853system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses |
| 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses | 855system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses |
| 856system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses 857system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses 858system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses 859system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses 860system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency 861system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency 862system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency 863system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency 864system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency 865system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency 867system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency | 857system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses 858system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses 859system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses 860system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses 861system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency 862system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency 863system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency 866system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency 867system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency 868system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency |
| 868system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked 869system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 871system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 872system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked 873system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 874system.cpu.dcache.fast_writes 0 # number of fast writes performed 875system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 884system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 885system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 886system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 888system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 889system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 890system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 891system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses | 869system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked 870system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 872system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked 874system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu.dcache.fast_writes 0 # number of fast writes performed 876system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 885system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 886system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 889system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 890system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 891system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 892system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses |
| 892system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles 893system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles 900system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses 901system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses | 893system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles 901system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses 902system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses |
| 902system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 903system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses | 903system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 904system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses |
| 904system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses 905system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses 906system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses 907system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses 908system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency 910system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency 912system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency 914system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency | 905system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses 906system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses 907system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses 908system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency 910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency |
| 916system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 917 918---------- End Simulation Statistics ---------- | 917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 918 919---------- End Simulation Statistics ---------- |