| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated |
| 4sim_ticks 19079500 # Number of ticks simulated 5final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 19030500 # Number of ticks simulated 5final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 82615 # Simulator instruction rate (inst/s) 8host_op_rate 82599 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 272039638 # Simulator tick rate (ticks/s) | 7host_inst_rate 79159 # Simulator instruction rate (inst/s) 8host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 259986612 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 262500 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 446 # Number of read requests responded to by this memory | 10host_mem_usage 262500 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 446 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 446 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 446 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 18951000 # Total gap between requests | 78system.physmem.totGap 18902000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 446 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 446 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation 202system.physmem.totQLat 2851500 # Total ticks spent queuing 203system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation 202system.physmem.totQLat 3599250 # Total ticks spent queuing 203system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers | 204system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers |
| 205system.physmem.totBankLat 6902500 # Total ticks spent accessing banks 206system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst 207system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst | 205system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s | 207system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s | 210system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 11.69 # Data bus utilization in percentage 216system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads | 213system.physmem.busUtil 11.72 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing | 216system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 358 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 358 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 42491.03 # Average gap between requests | 222system.physmem.avgGap 42381.17 # Average gap between requests |
| 225system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined | 223system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined |
| 226system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 227system.membus.throughput 1496055976 # Throughput (bytes/s) | 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 229system.membus.throughput 1499908042 # Throughput (bytes/s) |
| 228system.membus.trans_dist::ReadReq 399 # Transaction distribution 229system.membus.trans_dist::ReadResp 399 # Transaction distribution 230system.membus.trans_dist::ReadExReq 47 # Transaction distribution 231system.membus.trans_dist::ReadExResp 47 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 28544 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 230system.membus.trans_dist::ReadReq 399 # Transaction distribution 231system.membus.trans_dist::ReadResp 399 # Transaction distribution 232system.membus.trans_dist::ReadExReq 47 # Transaction distribution 233system.membus.trans_dist::ReadExResp 47 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 28544 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 238system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks) | 240system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) |
| 239system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) | 241system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) |
| 240system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 21.9 # Layer utilization (%) | 242system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) 243system.membus.respLayer1.utilization 22.0 # Layer utilization (%) |
| 242system.cpu_clk_domain.clock 500 # Clock period in ticks 243system.cpu.branchPred.lookups 2235 # Number of BP lookups 244system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted 245system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect 246system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups 247system.cpu.branchPred.BTBHits 602 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 249system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage --- 13 unchanged lines hidden (view full) --- 263system.cpu.itb.read_accesses 0 # DTB read accesses 264system.cpu.itb.write_hits 0 # DTB write hits 265system.cpu.itb.write_misses 0 # DTB write misses 266system.cpu.itb.write_accesses 0 # DTB write accesses 267system.cpu.itb.hits 0 # DTB hits 268system.cpu.itb.misses 0 # DTB misses 269system.cpu.itb.accesses 0 # DTB accesses 270system.cpu.workload.num_syscalls 9 # Number of system calls | 244system.cpu_clk_domain.clock 500 # Clock period in ticks 245system.cpu.branchPred.lookups 2235 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted 247system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect 248system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 602 # Number of BTB hits 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 251system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage --- 13 unchanged lines hidden (view full) --- 265system.cpu.itb.read_accesses 0 # DTB read accesses 266system.cpu.itb.write_hits 0 # DTB write hits 267system.cpu.itb.write_misses 0 # DTB write misses 268system.cpu.itb.write_accesses 0 # DTB write accesses 269system.cpu.itb.hits 0 # DTB hits 270system.cpu.itb.misses 0 # DTB misses 271system.cpu.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 9 # Number of system calls |
| 271system.cpu.numCycles 38160 # number of cpu cycles simulated | 273system.cpu.numCycles 38062 # number of cpu cycles simulated |
| 272system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 273system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 274system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 275system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 274system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss | 276system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss |
| 275system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed 276system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered 277system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken 278system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked 279system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing | 277system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed 278system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered 279system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken 280system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked 281system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing |
| 280system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked | 282system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked |
| 281system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched 282system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed | 283system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched 284system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed |
| 283system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) |
| 286system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 288system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 287system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total) | 289system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) |
| 296system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 298system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle 301system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle 302system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle 303system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked 304system.cpu.decode.RunCycles 2094 # Number of cycles decode is running 305system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking | 301system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle 303system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle 304system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle 305system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked 306system.cpu.decode.RunCycles 2089 # Number of cycles decode is running 307system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking |
| 306system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing 307system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch 308system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction 309system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode 310system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode 311system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing | 308system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing 309system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch 310system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction 311system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode 312system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode 313system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing |
| 312system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle 313system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking | 314system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle 315system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking |
| 314system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst | 316system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst |
| 315system.cpu.rename.RunCycles 1984 # Number of cycles rename is running 316system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking | 317system.cpu.rename.RunCycles 1980 # Number of cycles rename is running 318system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking |
| 317system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename 318system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full | 319system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename 320system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full |
| 319system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full | 321system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full |
| 320system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed 321system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made 322system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups 323system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 324system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 325system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing 326system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 327system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 322system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed 323system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made 324system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups 325system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 326system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 327system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing 328system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 329system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 328system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer | 330system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer |
| 329system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. 330system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 331system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 332system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. 333system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) 334system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ 335system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued 336system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued 337system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling 338system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph 339system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed | 331system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. 332system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 333system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 334system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. 335system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) 336system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ 337system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued 338system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued 339system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling 340system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph 341system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed |
| 340system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle | 342system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle |
| 343system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 344system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle | 346system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle |
| 351system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 356system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle | 358system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle |
| 357system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 418system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued 421system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued 422system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::total 8901 # Type of FU issued | 359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued 423system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued 424system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 427system.cpu.iq.FU_type_0::total 8901 # Type of FU issued |
| 426system.cpu.iq.rate 0.233255 # Inst issue rate | 428system.cpu.iq.rate 0.233855 # Inst issue rate |
| 427system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 428system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) | 429system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 430system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) |
| 429system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads | 431system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads |
| 430system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes 431system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses 432system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 433system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 434system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 435system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses 436system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 437system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 462system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions 463system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed 464system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute 465system.cpu.iew.exec_swp 0 # number of swp insts executed 466system.cpu.iew.exec_nop 0 # number of nop insts executed 467system.cpu.iew.exec_refs 3201 # number of memory reference insts executed 468system.cpu.iew.exec_branches 1350 # Number of branches executed 469system.cpu.iew.exec_stores 1523 # Number of stores executed | 432system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes 433system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses 434system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 435system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 436system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 437system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses 438system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 439system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 464system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions 465system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed 466system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute 467system.cpu.iew.exec_swp 0 # number of swp insts executed 468system.cpu.iew.exec_nop 0 # number of nop insts executed 469system.cpu.iew.exec_refs 3201 # number of memory reference insts executed 470system.cpu.iew.exec_branches 1350 # Number of branches executed 471system.cpu.iew.exec_stores 1523 # Number of stores executed |
| 470system.cpu.iew.exec_rate 0.222746 # Inst execution rate | 472system.cpu.iew.exec_rate 0.223320 # Inst execution rate |
| 471system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit 472system.cpu.iew.wb_count 8155 # cumulative count of insts written-back | 473system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit 474system.cpu.iew.wb_count 8155 # cumulative count of insts written-back |
| 473system.cpu.iew.wb_producers 4217 # num instructions producing a value 474system.cpu.iew.wb_consumers 6678 # num instructions consuming a value | 475system.cpu.iew.wb_producers 4187 # num instructions producing a value 476system.cpu.iew.wb_consumers 6623 # num instructions consuming a value |
| 475system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 477system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 476system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle 477system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back | 478system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle 479system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back |
| 478system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 479system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit 480system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 481system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted | 480system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 481system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit 482system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 483system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted |
| 482system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle | 484system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle |
| 485system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 487system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 486system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle | 488system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle |
| 495system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 497system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 498system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle |
| 499system.cpu.commit.committedInsts 5792 # Number of instructions committed 500system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 501system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 502system.cpu.commit.refs 2007 # Number of memory references committed 503system.cpu.commit.loads 961 # Number of loads committed 504system.cpu.commit.membars 7 # Number of memory barriers committed 505system.cpu.commit.branches 1037 # Number of branches committed 506system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 507system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 508system.cpu.commit.function_calls 103 # Number of function calls committed. | 501system.cpu.commit.committedInsts 5792 # Number of instructions committed 502system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 503system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 504system.cpu.commit.refs 2007 # Number of memory references committed 505system.cpu.commit.loads 961 # Number of loads committed 506system.cpu.commit.membars 7 # Number of memory barriers committed 507system.cpu.commit.branches 1037 # Number of branches committed 508system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 509system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 510system.cpu.commit.function_calls 103 # Number of function calls committed. |
| 511system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 512system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction 513system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction 514system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction 515system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction 516system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction 517system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction 518system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction 519system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction 520system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 542system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 543system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 544system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 545system.cpu.commit.op_class_0::total 5792 # Class of committed instruction |
|
| 509system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached 510system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 546system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached 547system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 511system.cpu.rob.rob_reads 21343 # The number of ROB reads | 548system.cpu.rob.rob_reads 21428 # The number of ROB reads |
| 512system.cpu.rob.rob_writes 21442 # The number of ROB writes | 549system.cpu.rob.rob_writes 21442 # The number of ROB writes |
| 513system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself 514system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling | 550system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself 551system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 515system.cpu.committedInsts 5792 # Number of Instructions Simulated 516system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 517system.cpu.committedInsts_total 5792 # Number of Instructions Simulated | 552system.cpu.committedInsts 5792 # Number of Instructions Simulated 553system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 554system.cpu.committedInsts_total 5792 # Number of Instructions Simulated |
| 518system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction 519system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads 520system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle 521system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads | 555system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction 556system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads 557system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle 558system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads |
| 522system.cpu.int_regfile_reads 13470 # number of integer regfile reads 523system.cpu.int_regfile_writes 7047 # number of integer regfile writes 524system.cpu.fp_regfile_reads 25 # number of floating regfile reads 525system.cpu.fp_regfile_writes 2 # number of floating regfile writes | 559system.cpu.int_regfile_reads 13470 # number of integer regfile reads 560system.cpu.int_regfile_writes 7047 # number of integer regfile writes 561system.cpu.fp_regfile_reads 25 # number of floating regfile reads 562system.cpu.fp_regfile_writes 2 # number of floating regfile writes |
| 526system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s) | 563system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) |
| 527system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution 528system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution 529system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 530system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 531system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) 532system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 533system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) 534system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) 535system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 536system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) 537system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) 538system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 539system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 540system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 564system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 568system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) 569system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) 572system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) 575system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 576system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 577system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 541system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks) | 578system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) |
| 542system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) | 579system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) |
| 543system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) 544system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 580system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) 581system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 545system.cpu.icache.tags.replacements 0 # number of replacements | 582system.cpu.icache.tags.replacements 0 # number of replacements |
| 546system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use | 583system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use |
| 547system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. 548system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. 549system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. 550system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 584system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. 585system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. 586system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. 587system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 551system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor 552system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy 553system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy | 588system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor 589system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy 590system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy |
| 554system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 555system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 556system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 557system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id 558system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses 559system.cpu.icache.tags.data_accesses 3971 # Number of data accesses 560system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits 561system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits 562system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits 563system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits 564system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits 565system.cpu.icache.overall_hits::total 1369 # number of overall hits 566system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses 567system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses 568system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses 569system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses 570system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses 571system.cpu.icache.overall_misses::total 441 # number of overall misses | 591system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 593system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 594system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id 595system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses 596system.cpu.icache.tags.data_accesses 3971 # Number of data accesses 597system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits 602system.cpu.icache.overall_hits::total 1369 # number of overall hits 603system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses 608system.cpu.icache.overall_misses::total 441 # number of overall misses |
| 572system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles 573system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles 574system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles 575system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles 576system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles 577system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles | 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles |
| 578system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) 579system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) 580system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses 581system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses 582system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses 583system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses 584system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses 585system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses 586system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses 587system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses 588system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses 589system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses | 615system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses |
| 590system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency 591system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency 592system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency 593system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency 594system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency 595system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency | 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency |
| 596system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked 597system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 599system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked 601system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.icache.fast_writes 0 # number of fast writes performed 603system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 608system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 609system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 610system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 611system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 612system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 613system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 614system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 615system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses | 633system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.fast_writes 0 # number of fast writes performed 640system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 645system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 646system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 647system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 648system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 649system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 650system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 651system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 652system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses |
| 616system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles 617system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles 621system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles | 653system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles 654system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles 655system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles 658system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles |
| 622system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses 623system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses 624system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses 625system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses 626system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses 627system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses | 659system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses 661system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses 662system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses 663system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses 664system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses |
| 628system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency 629system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency 630system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency 631system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency 632system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency 633system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency | 665system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency 666system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency 667system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency 668system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency 669system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency |
| 634system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 635system.cpu.l2cache.tags.replacements 0 # number of replacements | 671system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 672system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 636system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use | 673system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use |
| 637system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 638system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 639system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. 640system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 674system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 675system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 676system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. 677system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 641system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor 642system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor 643system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy | 678system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy |
| 644system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy | 681system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy |
| 645system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy | 682system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy |
| 646system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id 647system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id 648system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id 649system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 650system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses 651system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses 652system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 653system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 664system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 665system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 666system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 667system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 668system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 669system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 670system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 671system.cpu.l2cache.overall_misses::total 446 # number of overall misses | 683system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id 686system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 687system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses 688system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses 689system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 690system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 701system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 702system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 703system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 705system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 706system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 707system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 708system.cpu.l2cache.overall_misses::total 446 # number of overall misses |
| 672system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles 673system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles 677system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles 678system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles 679system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles 680system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles 681system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles 682system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles | 709system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles 710system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles 712system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles 713system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles 716system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles |
| 683system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 684system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 685system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 686system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 687system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 688system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 689system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 690system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 698system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses | 720system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 725system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 726system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 727system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 736system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 739system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 740system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 741system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses |
| 705system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency 706system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency 707system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency 708system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency 709system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency 710system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency 713system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency | 742system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency 743system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency 744system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency 745system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency 746system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency 747system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency 748system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency 749system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency 750system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency 752system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency |
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| 735system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles 736system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles 737system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles 738system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles 739system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles 740system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles 741system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles 742system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles 743system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles 744system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles 745system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles | 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles |
| 746system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 749system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 750system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 751system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 752system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 753system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 754system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 755system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 756system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses | 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses |
| 757system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency 758system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency 759system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency 760system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency 761system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency 762system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency 763system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency 764system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency 765system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency 766system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency 767system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency | 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency |
| 768system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.cpu.dcache.tags.replacements 0 # number of replacements | 805system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.dcache.tags.replacements 0 # number of replacements |
| 770system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use | 807system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use |
| 771system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. 772system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 773system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. 774system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 808system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. 809system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 810system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. 811system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 775system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor | 812system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor |
| 776system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy 777system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy 778system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 779system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 780system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 781system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 782system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses 783system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 792system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 793system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses 794system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses 795system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses 796system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses 797system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses 798system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses 799system.cpu.dcache.overall_misses::total 435 # number of overall misses | 813system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy 814system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy 815system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 816system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 817system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 818system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 819system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses 820system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 829system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 830system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses 831system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses 832system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses 833system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses 834system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses 835system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses 836system.cpu.dcache.overall_misses::total 435 # number of overall misses |
| 800system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles 801system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles 802system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles 803system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles 804system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles 805system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles 806system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles 807system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles | 837system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles 838system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles 839system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles 840system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles 841system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles |
| 808system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) 809system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) 810system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 811system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 812system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses 813system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses 814system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses 815system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses 816system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses 817system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses 818system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses 819system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses 820system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses 821system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses 822system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses 823system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses | 845system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 849system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses 850system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses 851system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses 852system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses 853system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses 855system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses 857system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses 858system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses 859system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses 860system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses |
| 824system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency 825system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency 827system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency 828system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency 829system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency 830system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency 831system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency 832system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked | 861system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency 862system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency 863system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency 866system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency 867system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency 868system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency 869system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked |
| 833system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 834system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 835system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 870system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 872system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 836system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked | 873system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked |
| 837system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838system.cpu.dcache.fast_writes 0 # number of fast writes performed 839system.cpu.dcache.cache_copies 0 # number of cache copies performed 840system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 841system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits 842system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 843system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 844system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 845system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 846system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 847system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits 848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 849system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 851system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 852system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 853system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 854system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 855system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses | 874system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu.dcache.fast_writes 0 # number of fast writes performed 876system.cpu.dcache.cache_copies 0 # number of cache copies performed 877system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 878system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits 879system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 881system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits 882system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits 883system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits 884system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits 885system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 886system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 889system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 890system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 891system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 892system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses |
| 856system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles 857system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles 858system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles 859system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles 860system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles 861system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles 862system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles 863system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles | 893system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles |
| 864system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses 865system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses 866system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 867system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 868system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses 869system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses 870system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses 871system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses | 901system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses 902system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses 903system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 904system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 905system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses 906system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses 907system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses 908system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses |
| 872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency 873system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency 874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency 875system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency 876system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency 877system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency 878system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency 879system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency | 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency 910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency |
| 880system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 881 882---------- End Simulation Statistics ---------- | 917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 918 919---------- End Simulation Statistics ---------- |