7,10c7,10
< host_inst_rate 73653 # Simulator instruction rate (inst/s)
< host_op_rate 73641 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 142731766 # Simulator tick rate (ticks/s)
< host_mem_usage 211540 # Number of bytes of host memory used
---
> host_inst_rate 72271 # Simulator instruction rate (inst/s)
> host_op_rate 72256 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 140039967 # Simulator tick rate (ticks/s)
> host_mem_usage 211876 # Number of bytes of host memory used
14,22c14,29
< system.physmem.bytes_read 28736 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 449 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s)
341a349
> system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses
342a351
> system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses
343a353
> system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses
344a355
> system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency
345a357
> system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency
346a359
> system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency
373a387
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses
374a389
> system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses
375a391
> system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses
376a393
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency
377a395
> system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency
378a397
> system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency
421a441
> system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses
422a443
> system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses
423a445
> system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses
424a447
> system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses
425a449
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency
426a451
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency
427a453
> system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency
428a455
> system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency
461a489
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses
462a491
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses
463a493
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses
464a495
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses
465a497
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency
466a499
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency
467a501
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency
468a503
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency
521a557
> system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses
522a559
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
524a562
> system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses
526a565
> system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses
528a568
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency
529a570
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency
531a573
> system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency
533a576
> system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency
565a609
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses
566a611
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
568a614
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses
570a617
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses
572a620
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency
573a622
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency
575a625
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency
577a628
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency
< host_inst_rate 73653 # Simulator instruction rate (inst/s)
< host_op_rate 73641 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 142731766 # Simulator tick rate (ticks/s)
< host_mem_usage 211540 # Number of bytes of host memory used
---
> host_inst_rate 72271 # Simulator instruction rate (inst/s)
> host_op_rate 72256 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 140039967 # Simulator tick rate (ticks/s)
> host_mem_usage 211876 # Number of bytes of host memory used
14,22c14,29
< system.physmem.bytes_read 28736 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 449 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s)
341a349
> system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses
342a351
> system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses
343a353
> system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses
344a355
> system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency
345a357
> system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency
346a359
> system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency
373a387
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses
374a389
> system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses
375a391
> system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses
376a393
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency
377a395
> system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency
378a397
> system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency
421a441
> system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses
422a443
> system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses
423a445
> system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses
424a447
> system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses
425a449
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency
426a451
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency
427a453
> system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency
428a455
> system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency
461a489
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses
462a491
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses
463a493
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses
464a495
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses
465a497
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency
466a499
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency
467a501
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency
468a503
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency
521a557
> system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses
522a559
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
524a562
> system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses
526a565
> system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses
528a568
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency
529a570
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency
531a573
> system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency
533a576
> system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency
565a609
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses
566a611
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
568a614
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses
570a617
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses
572a620
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency
573a622
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency
575a625
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency
577a628
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency