3,5c3,5
< sim_seconds 0.000020 # Number of seconds simulated
< sim_ticks 20159000 # Number of ticks simulated
< final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000021 # Number of seconds simulated
> sim_ticks 21268000 # Number of ticks simulated
> final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 70194 # Simulator instruction rate (inst/s)
< host_op_rate 70182 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 244226628 # Simulator tick rate (ticks/s)
< host_mem_usage 249960 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 112778 # Simulator instruction rate (inst/s)
> host_op_rate 112739 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 413846380 # Simulator tick rate (ticks/s)
> host_mem_usage 248372 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1032160993 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 300921572 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1333082565 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1032160993 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1032160993 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1032160993 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 300921572 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1333082565 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 20108500 # Total gap between requests
---
> system.physmem.totGap 21217500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see
98c98
< system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
190,204c190,205
< system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
< system.physmem.totQLat 3790750 # Total ticks spent queuing
< system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 351.573333 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 215.062906 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 340.509998 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 23 30.67% 30.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18 24.00% 54.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11 14.67% 69.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2 2.67% 72.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.00% 76.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 4 5.33% 81.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 2.67% 84.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 4.00% 88.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 12.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
> system.physmem.totQLat 5980000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14323750 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13438.20 # Average queueing delay per DRAM burst
208,209c209,210
< system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32188.20 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1339.10 # Average DRAM read bandwidth in MiByte/s
211c212
< system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1339.10 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.physmem.busUtil 11.04 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.46 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.46 # Data bus utilization in percentage for reads
217c218
< system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
223c224
< system.physmem.avgGap 45187.64 # Average gap between requests
---
> system.physmem.avgGap 47679.78 # Average gap between requests
225,227c226,228
< system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ)
---
> system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ)
229,234c230,239
< system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ)
< system.physmem_0.averagePower 947.872361 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
---
> system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3922170 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5666370 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 14570505 # Total energy per rank (pJ)
> system.physmem_0.averagePower 685.066353 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 12593250 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states
236,241c241,247
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 167250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 8137250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12426000 # Time in different power states
> system.physmem_1.actEnergy 78540 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 30360 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ)
243,248c249,258
< system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ)
< system.physmem_1.averagePower 747.441023 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states
---
> system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 747840 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1408800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 6431880 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 10938900 # Total energy per rank (pJ)
> system.physmem_1.averagePower 514.317955 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 13775500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3585000 # Time in different power states
250,255c260,266
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2407 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted
---
> system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 1201500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 14106750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2411 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1982 # Number of conditional branches predicted
257,258c268,269
< system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 691 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 2056 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 693 # Number of BTB hits
260,261c271,272
< system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 33.706226 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target.
287,288c298,299
< system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 40319 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 21268000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 42537 # number of cpu cycles simulated
291,296c302,307
< system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 7672 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 4149 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 849 # Number of cycles fetch has spent squashing
300,304c311,315
< system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 12418 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.076582 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.475981 # Number of instructions fetched each cycle (Total)
306,314c317,325
< system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10084 81.20% 81.20% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 214 1.72% 84.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 148 1.19% 92.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 988 7.96% 100.00% # Number of instructions fetched each cycle (Total)
318,326c329,337
< system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 1948 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch
---
> system.cpu.fetch.rateDist::total 12418 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7245 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 1946 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 276 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 324 # Number of times decode resolved a branch
330,336c341,347
< system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 1896 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename
---
> system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 7413 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 1897 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11042 # Number of instructions processed by rename
339c350
< system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 1522 # Number of times rename has blocked due to SQ full
341,342c352,353
< system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups
---
> system.cpu.rename.RenameLookups 17897 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 17871 # Number of integer rename lookups
348,350c359,361
< system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 381 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 1937 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1590 # Number of stores inserted to the mem dependence unit.
353c364
< system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec)
355c366
< system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8808 # Number of instructions issued
357,358c368,369
< system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph
360,362c371,373
< system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 12418 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.709293 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.511827 # Number of insts issued each cycle
364,372c375,383
< system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9303 74.92% 74.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 429 3.45% 95.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 293 2.36% 97.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 212 1.71% 99.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 64 0.52% 99.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Number of insts issued each cycle
376c387
< system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle
378,408c389,419
< system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 12 6.32% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 88 46.32% 52.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 90 47.37% 100.00% # attempts to use FU when none available
412,442c423,453
< system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5530 62.78% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1813 20.58% 83.39% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1463 16.61% 100.00% # Type of FU issued
445,451c456,462
< system.cpu.iq.FU_type_0::total 8810 # Type of FU issued
< system.cpu.iq.rate 0.218507 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 189 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8808 # Type of FU issued
> system.cpu.iq.rate 0.207067 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 190 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.021571 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30215 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses
455c466
< system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8964 # Number of integer alu accesses
457c468
< system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores
459c470
< system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed
461,462c472,473
< system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 544 # Number of stores squashed
468,471c479,482
< system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 276 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 722 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 71 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ
473,474c484,485
< system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 1937 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1590 # Number of dispatched store instructions
477,478c488,489
< system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
---
> system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
482,484c493,495
< system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 8463 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1703 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 345 # Number of squashed instructions skipped in execute
487,497c498,508
< system.cpu.iew.exec_refs 3077 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1359 # Number of branches executed
< system.cpu.iew.exec_stores 1378 # Number of stores executed
< system.cpu.iew.exec_rate 0.209827 # Inst execution rate
< system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 8139 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 4432 # num instructions producing a value
< system.cpu.iew.wb_consumers 7119 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3080 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1358 # Number of branches executed
> system.cpu.iew.exec_stores 1377 # Number of stores executed
> system.cpu.iew.exec_rate 0.198956 # Inst execution rate
> system.cpu.iew.wb_sent 8242 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 8142 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 4448 # num instructions producing a value
> system.cpu.iew.wb_consumers 7158 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.191410 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.621403 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
500,502c511,513
< system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 11716 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.494367 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.358573 # Number of insts commited each cycle
504,510c515,521
< system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 9551 81.52% 81.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 850 7.26% 88.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 527 4.50% 93.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 215 1.84% 95.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle
516c527
< system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11716 # Number of insts commited each cycle
563,566c574,577
< system.cpu.rob.rob_reads 21857 # The number of ROB reads
< system.cpu.rob.rob_writes 21183 # The number of ROB writes
< system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 21842 # The number of ROB reads
> system.cpu.rob.rob_writes 21175 # The number of ROB writes
> system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 30119 # Total number of cycles that the CPU has spent unscheduled due to idling
569,574c580,585
< system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 13369 # number of integer regfile reads
< system.cpu.int_regfile_writes 7149 # number of integer regfile writes
---
> system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.344095 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.136164 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.136164 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 13368 # number of integer regfile reads
> system.cpu.int_regfile_writes 7153 # number of integer regfile writes
577c588
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
579,580c590,591
< system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 64.389343 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2206 # Total number of references to valid blocks.
582c593
< system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 21.627451 # Average number of references to valid blocks.
584,586c595,597
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.389343 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.015720 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.015720 # Average percentage of cache occupancy
588,589c599,600
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
591,601c602,612
< system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits
< system.cpu.dcache.overall_hits::total 2199 # number of overall hits
---
> system.cpu.dcache.tags.tag_accesses 5390 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5390 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1485 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1485 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits
> system.cpu.dcache.overall_hits::total 2206 # number of overall hits
604,619c615,630
< system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses
< system.cpu.dcache.overall_misses::total 437 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses
> system.cpu.dcache.overall_misses::total 438 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8211000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8211000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 32489496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 32489496 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 40700496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 40700496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 40700496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 40700496 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1598 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses)
622,642c633,653
< system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 2644 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2644 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2644 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2644 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070713 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070713 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.165658 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.165658 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.165658 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.165658 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 92923.506849 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 92923.506849 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 612 # number of cycles access was blocked
646c657
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 102 # average number of cycles each access was blocked
650,655c661,666
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits
664,673c675,684
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4669500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4669500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4693998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4693998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9363498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9363498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9363498 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9363498 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035670 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035670 # mshr miss rate for ReadReq accesses
676,688c687,699
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.039334 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.039334 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
690,691c701,702
< system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 168.912200 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1425 # Total number of references to valid blocks.
693c704
< system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.083095 # Average number of references to valid blocks.
695,697c706,708
< system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 168.912200 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082477 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082477 # Average percentage of cache occupancy
699,700c710,711
< system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
702,710c713,721
< system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4059 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits
< system.cpu.icache.overall_hits::total 1419 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4071 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4071 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1425 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1425 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1425 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1425 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1425 # number of overall hits
> system.cpu.icache.overall_hits::total 1425 # number of overall hits
717,741c728,752
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 33901500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 33901500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 33901500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 33901500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 33901500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 33901500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1861 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1861 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1861 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1861 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234283 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.234283 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.234283 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.234283 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.234283 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.234283 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77755.733945 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77755.733945 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked
745c756
< system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 113.400000 # average number of cycles each access was blocked
759,777c770,788
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28298000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28298000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28298000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28298000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28298000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28298000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188071 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.188071 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.188071 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
779c790
< system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 231.224808 # Cycle average of tags in use
784,788c795,799
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.706281 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 63.518527 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001938 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007056 # Average percentage of cache occupancy
790,791c801,802
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
795c806
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
818,829c829,840
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4620000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27705000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27705000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4563000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4563000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27705000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9183000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36888000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27705000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9183000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36888000 # number of overall miss cycles
854,865c865,876
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179 # average overall miss latency
884,895c895,906
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24275000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24275000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4033000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4033000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24275000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8183000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 32458000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24275000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8183000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 32458000 # number of overall MSHR miss cycles
908,919c919,930
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency
926c937
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
954c965
< system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
956c967
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
963c974
< system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states
984,987c995,998
< system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2325250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 10.9 # Layer utilization (%)