4,5c4,5
< sim_ticks 19908000 # Number of ticks simulated
< final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 20159000 # Number of ticks simulated
> final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 79311 # Simulator instruction rate (inst/s)
< host_op_rate 79299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 272523705 # Simulator tick rate (ticks/s)
< host_mem_usage 246096 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 70194 # Simulator instruction rate (inst/s)
> host_op_rate 70182 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244226628 # Simulator tick rate (ticks/s)
> host_mem_usage 249960 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 19857500 # Total gap between requests
---
> system.physmem.totGap 20108500 # Total gap between requests
192,196c192,196
< system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation
200,202c200,201
< system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation
204,205c203,204
< system.physmem.totQLat 3759500 # Total ticks spent queuing
< system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3790750 # Total ticks spent queuing
> system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM
207c206
< system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst
209,210c208,209
< system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s
212c211
< system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.physmem.busUtil 11.18 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.04 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads
224c223
< system.physmem.avgGap 44623.60 # Average gap between requests
---
> system.physmem.avgGap 45187.64 # Average gap between requests
228c227
< system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ)
231,234c230,233
< system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ)
< system.physmem_0.averagePower 949.326386 # Core power per rank (mW)
---
> system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ)
> system.physmem_0.averagePower 947.872361 # Core power per rank (mW)
238c237
< system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states
245,249c244,248
< system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ)
< system.physmem_1.averagePower 748.316438 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states
---
> system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ)
> system.physmem_1.averagePower 747.441023 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states
252c251
< system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states
254c253
< system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
288,289c287,288
< system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 39817 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 40319 # number of cpu cycles simulated
292,293c291,292
< system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed
296c295
< system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked
301,305c300,304
< system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total)
307,315c306,314
< system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total)
319,323c318,322
< system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked
329,330c328,329
< system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode
332,337c331,336
< system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 1898 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 1896 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename
340,343c339,342
< system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups
346c345
< system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing
349c348
< system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer
351c350
< system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
354c353
< system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec)
356c355
< system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued
358,359c357,358
< system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph
361,363c360,362
< system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle
365,373c364,372
< system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle
377c376
< system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle
416,442c415,441
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued
446,447c445,446
< system.cpu.iq.FU_type_0::total 8811 # Type of FU issued
< system.cpu.iq.rate 0.221287 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8810 # Type of FU issued
> system.cpu.iq.rate 0.218507 # Inst issue rate
449,451c448,450
< system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes
---
> system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes
456c455
< system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses
463c462
< system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed
470c469
< system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking
472c471
< system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ
475c474
< system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
485c484
< system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute
489c488
< system.cpu.iew.exec_branches 1357 # Number of branches executed
---
> system.cpu.iew.exec_branches 1359 # Number of branches executed
491c490
< system.cpu.iew.exec_rate 0.212472 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.209827 # Inst execution rate
494,498c493,497
< system.cpu.iew.wb_producers 4434 # num instructions producing a value
< system.cpu.iew.wb_consumers 7122 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_producers 4432 # num instructions producing a value
> system.cpu.iew.wb_consumers 7119 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit
501,503c500,502
< system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle
505,513c504,512
< system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle
517c516
< system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle
564,567c563,566
< system.cpu.rob.rob_reads 21317 # The number of ROB reads
< system.cpu.rob.rob_writes 21174 # The number of ROB writes
< system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 21857 # The number of ROB reads
> system.cpu.rob.rob_writes 21183 # The number of ROB writes
> system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling
570,575c569,574
< system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 13370 # number of integer regfile reads
< system.cpu.int_regfile_writes 7150 # number of integer regfile writes
---
> system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 13369 # number of integer regfile reads
> system.cpu.int_regfile_writes 7149 # number of integer regfile writes
578c577
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
580c579
< system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use
585,587c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy
589,590c588,589
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id
594c593
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
611,618c610,617
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles
635,643c634,642
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
647c646
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked
665,672c664,671
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles
681,689c680,688
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
691,692c690,691
< system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks.
694c693
< system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks.
696,698c695,697
< system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy
700,701c699,700
< system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
703,711c702,710
< system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4061 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits
< system.cpu.icache.overall_hits::total 1420 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4059 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits
> system.cpu.icache.overall_hits::total 1419 # number of overall hits
718,742c717,741
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked
746c745
< system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked
760,778c759,777
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
780c779
< system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use
782,783c781,782
< system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks.
785,793c784,792
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id
796c795
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
819,830c818,829
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles
855,866c854,865
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency
885,896c884,895
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles
909,920c908,919
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
927c926
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
958c957,963
< system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
980,982c985,987
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
< sim_ticks 19908000 # Number of ticks simulated
< final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 20159000 # Number of ticks simulated
> final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 79311 # Simulator instruction rate (inst/s)
< host_op_rate 79299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 272523705 # Simulator tick rate (ticks/s)
< host_mem_usage 246096 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 70194 # Simulator instruction rate (inst/s)
> host_op_rate 70182 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244226628 # Simulator tick rate (ticks/s)
> host_mem_usage 249960 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 19857500 # Total gap between requests
---
> system.physmem.totGap 20108500 # Total gap between requests
192,196c192,196
< system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation
200,202c200,201
< system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation
204,205c203,204
< system.physmem.totQLat 3759500 # Total ticks spent queuing
< system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3790750 # Total ticks spent queuing
> system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM
207c206
< system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst
209,210c208,209
< system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s
212c211
< system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.physmem.busUtil 11.18 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.04 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads
224c223
< system.physmem.avgGap 44623.60 # Average gap between requests
---
> system.physmem.avgGap 45187.64 # Average gap between requests
228c227
< system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ)
231,234c230,233
< system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ)
< system.physmem_0.averagePower 949.326386 # Core power per rank (mW)
---
> system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ)
> system.physmem_0.averagePower 947.872361 # Core power per rank (mW)
238c237
< system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states
245,249c244,248
< system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ)
< system.physmem_1.averagePower 748.316438 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states
---
> system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ)
> system.physmem_1.averagePower 747.441023 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states
252c251
< system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states
254c253
< system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
288,289c287,288
< system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 39817 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 40319 # number of cpu cycles simulated
292,293c291,292
< system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed
296c295
< system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked
301,305c300,304
< system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total)
307,315c306,314
< system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total)
319,323c318,322
< system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked
329,330c328,329
< system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode
332,337c331,336
< system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 1898 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 1896 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename
340,343c339,342
< system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups
346c345
< system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing
349c348
< system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer
351c350
< system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
354c353
< system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec)
356c355
< system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued
358,359c357,358
< system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph
361,363c360,362
< system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle
365,373c364,372
< system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle
377c376
< system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle
416,442c415,441
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued
446,447c445,446
< system.cpu.iq.FU_type_0::total 8811 # Type of FU issued
< system.cpu.iq.rate 0.221287 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8810 # Type of FU issued
> system.cpu.iq.rate 0.218507 # Inst issue rate
449,451c448,450
< system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes
---
> system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes
456c455
< system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses
463c462
< system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed
470c469
< system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking
472c471
< system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ
475c474
< system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
485c484
< system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute
489c488
< system.cpu.iew.exec_branches 1357 # Number of branches executed
---
> system.cpu.iew.exec_branches 1359 # Number of branches executed
491c490
< system.cpu.iew.exec_rate 0.212472 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.209827 # Inst execution rate
494,498c493,497
< system.cpu.iew.wb_producers 4434 # num instructions producing a value
< system.cpu.iew.wb_consumers 7122 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_producers 4432 # num instructions producing a value
> system.cpu.iew.wb_consumers 7119 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit
501,503c500,502
< system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle
505,513c504,512
< system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle
517c516
< system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle
564,567c563,566
< system.cpu.rob.rob_reads 21317 # The number of ROB reads
< system.cpu.rob.rob_writes 21174 # The number of ROB writes
< system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 21857 # The number of ROB reads
> system.cpu.rob.rob_writes 21183 # The number of ROB writes
> system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling
570,575c569,574
< system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 13370 # number of integer regfile reads
< system.cpu.int_regfile_writes 7150 # number of integer regfile writes
---
> system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 13369 # number of integer regfile reads
> system.cpu.int_regfile_writes 7149 # number of integer regfile writes
578c577
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
580c579
< system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use
585,587c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy
589,590c588,589
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id
594c593
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
611,618c610,617
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles
635,643c634,642
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
647c646
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked
665,672c664,671
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles
681,689c680,688
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
691,692c690,691
< system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks.
694c693
< system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks.
696,698c695,697
< system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy
700,701c699,700
< system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
703,711c702,710
< system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4061 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits
< system.cpu.icache.overall_hits::total 1420 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4059 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits
> system.cpu.icache.overall_hits::total 1419 # number of overall hits
718,742c717,741
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked
746c745
< system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked
760,778c759,777
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
780c779
< system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use
782,783c781,782
< system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks.
785,793c784,792
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id
796c795
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
819,830c818,829
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles
855,866c854,865
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency
885,896c884,895
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles
909,920c908,919
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency
927c926
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
958c957,963
< system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states
980,982c985,987
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 11.6 # Layer utilization (%)