4,5c4,5
< sim_ticks 19923000 # Number of ticks simulated
< final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19908000 # Number of ticks simulated
> final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
17,18c17,18
< system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28352 # Number of bytes read from this memory
22,32c22,32
< system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 444 # Number of read requests accepted
---
> system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 443 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 445 # Number of read requests accepted
34c34
< system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::5 61 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 62 # Per bank write bursts
78c78
< system.physmem.totGap 19783500 # Total gap between requests
---
> system.physmem.totGap 19857500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 444 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 445 # Read request sizes (log2)
93,95c93,95
< system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see
190,196c190,196
< system.physmem.bytesPerActivate::mean 340.210526 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 203.437950 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 338.690117 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 26 34.21% 34.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 22.37% 56.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation
203,206c203,206
< system.physmem.totQLat 3746750 # Total ticks spent queuing
< system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 3759500 # Total ticks spent queuing
> system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 11.14 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.18 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing
219c219
< system.physmem.readRowHits 359 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 360 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads
223,224c223,224
< system.physmem.avgGap 44557.43 # Average gap between requests
< system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 44623.60 # Average gap between requests
> system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined
244,248c244,248
< system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ)
< system.physmem_1.averagePower 748.283278 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states
---
> system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ)
> system.physmem_1.averagePower 748.316438 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 2359 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 725 # Number of BTB hits
---
> system.cpu.branchPred.lookups 2407 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 691 # Number of BTB hits
259,261c259,265
< system.cpu.branchPred.BTBHitPct 36.579213 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 19 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 111 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches.
282c286
< system.cpu.numCycles 39847 # number of cpu cycles simulated
---
> system.cpu.numCycles 39817 # number of cpu cycles simulated
285,292c289,296
< system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 147 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps
294,298c298,302
< system.cpu.fetch.CacheLines 1822 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 12019 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.097263 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.493815 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total)
300,308c304,312
< system.cpu.fetch.rateDist::0 9698 80.69% 80.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 176 1.46% 82.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 221 1.84% 83.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 153 1.27% 85.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 238 1.98% 87.25% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total)
312,320c316,324
< system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 1924 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch
---
> system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 1948 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch
322,330c326,334
< system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 469 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 271 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 7350 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 927 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 518 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 1884 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1069 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 10932 # Number of instructions processed by rename
---
> system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 1898 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename
333,336c337,340
< system.cpu.rename.SQFullEvents 1028 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 9574 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 17720 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 17694 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups
339c343
< system.cpu.rename.UndoneMaps 4576 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing
342,347c346,351
< system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 1935 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1629 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 10141 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec)
349,352c353,356
< system.cpu.iq.iqInstsIssued 8840 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 4412 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph
354,356c358,360
< system.cpu.iq.issued_per_cycle::samples 12019 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.735502 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.540494 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle
358,365c362,369
< system.cpu.iq.issued_per_cycle::0 8914 74.17% 74.17% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 959 7.98% 82.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 649 5.40% 87.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 465 3.87% 91.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 426 3.54% 94.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 281 2.34% 97.30% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 228 1.90% 99.19% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 65 0.54% 99.73% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle
370c374
< system.cpu.iq.issued_per_cycle::total 12019 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle
372,402c376,406
< system.cpu.iq.fu_full::IntAlu 13 6.47% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 95 47.26% 53.73% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 93 46.27% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available
406,436c410,440
< system.cpu.iq.FU_type_0::IntAlu 5519 62.43% 62.43% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.43% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued
439,445c443,449
< system.cpu.iq.FU_type_0::total 8840 # Type of FU issued
< system.cpu.iq.rate 0.221849 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 201 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8811 # Type of FU issued
> system.cpu.iq.rate 0.221287 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 189 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses
449c453
< system.cpu.iq.int_alu_accesses 9007 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses
451c455
< system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores
453c457
< system.cpu.iew.lsq.thread0.squashedLoads 974 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed
455,456c459,460
< system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 583 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed
462,463c466,467
< system.cpu.iew.iewSquashCycles 271 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 843 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking
465,469c469,473
< system.cpu.iew.iewDispatchedInsts 10204 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 1935 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1629 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions
472,478c476,482
< system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 72 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 254 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 326 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute
481,491c485,495
< system.cpu.iew.exec_refs 3121 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1355 # Number of branches executed
< system.cpu.iew.exec_stores 1414 # Number of stores executed
< system.cpu.iew.exec_rate 0.212939 # Inst execution rate
< system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 8147 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 4452 # num instructions producing a value
< system.cpu.iew.wb_consumers 7114 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3077 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1357 # Number of branches executed
> system.cpu.iew.exec_stores 1378 # Number of stores executed
> system.cpu.iew.exec_rate 0.212472 # Inst execution rate
> system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 8139 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 4434 # num instructions producing a value
> system.cpu.iew.wb_consumers 7122 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
493,496c497,500
< system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle
498,506c502,510
< system.cpu.commit.committed_per_cycle::0 9160 80.89% 80.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 847 7.48% 88.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 528 4.66% 93.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 216 1.91% 94.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 182 1.61% 96.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 106 0.94% 97.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 122 1.08% 98.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 53 0.47% 99.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 110 0.97% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle
510c514
< system.cpu.commit.committed_per_cycle::total 11324 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle
557,560c561,564
< system.cpu.rob.rob_reads 21420 # The number of ROB reads
< system.cpu.rob.rob_writes 21108 # The number of ROB writes
< system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 21317 # The number of ROB reads
> system.cpu.rob.rob_writes 21174 # The number of ROB writes
> system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling
563,568c567,572
< system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 13452 # number of integer regfile reads
< system.cpu.int_regfile_writes 7138 # number of integer regfile writes
---
> system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 13370 # number of integer regfile reads
> system.cpu.int_regfile_writes 7150 # number of integer regfile writes
572,575c576,579
< system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks.
577,580c581,584
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
582,611c586,615
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1492 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1492 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 2213 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2213 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2213 # number of overall hits
< system.cpu.dcache.overall_hits::total 2213 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses
< system.cpu.dcache.overall_misses::total 433 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits
> system.cpu.dcache.overall_hits::total 2199 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses
> system.cpu.dcache.overall_misses::total 437 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses)
614,633c618,637
< system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency
---
> system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency
642,651c646,655
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses
654,667c658,671
< system.cpu.dcache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses
670,681c674,685
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
684,685c688,689
< system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks.
687c691
< system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks.
689,691c693,695
< system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy
696,733c700,737
< system.cpu.icache.tags.tag_accesses 3993 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 3993 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits
< system.cpu.icache.overall_hits::total 1389 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses
< system.cpu.icache.overall_misses::total 433 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1822 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1822 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1822 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.237651 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.237651 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4061 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits
> system.cpu.icache.overall_hits::total 1420 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses
> system.cpu.icache.overall_misses::total 436 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency
742,747c746,751
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 83 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
754,771c758,775
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
774c778
< system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use
776,777c780,781
< system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks.
779,784c783,788
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
786,789c790,793
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses
804,805c808,809
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 54 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 54 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses
807,808c811,812
< system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
810,823c814,827
< system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
< system.cpu.l2cache.overall_misses::total 445 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses
> system.cpu.l2cache.overall_misses::total 446 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles
828,829c832,833
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 56 # number of ReadSharedReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 57 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 57 # number of ReadSharedReq accesses(hits+misses)
831,832c835,836
< system.cpu.l2cache.demand_accesses::cpu.data 103 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 104 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses
834,835c838,839
< system.cpu.l2cache.overall_accesses::cpu.data 103 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 104 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses
840,841c844,845
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964286 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964286 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964912 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964912 # miss rate for ReadSharedReq accesses
843,844c847,848
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.980769 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.982379 # miss rate for demand accesses
846,859c850,863
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency
872,873c876,877
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 54 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 54 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses
875,876c879,880
< system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
878,891c882,895
< system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles
896,897c900,901
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses
899,900c903,904
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses
902,915c906,919
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
917c921
< system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter.
923c927
< system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
927c931
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution
932,933c936,937
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
935,937c939,941
< system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 454 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.017621 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.131715 # Request fanout histogram
939,940c943,944
< system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 446 98.24% 98.24% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 8 1.76% 100.00% # Request fanout histogram
945,946c949,950
< system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks)
950c954
< system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
952c956
< system.membus.trans_dist::ReadResp 397 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 396 # Transaction distribution
955c959
< system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution
---
> system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution
958,959c962,963
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes)
961c965
< system.membus.snoop_fanout::samples 444 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 445 # Request fanout histogram
965c969
< system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram
970,971c974,975
< system.membus.snoop_fanout::total 444 # Request fanout histogram
< system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 445 # Request fanout histogram
> system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks)
973,974c977,978
< system.membus.respLayer1.occupancy 2342750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.8 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 11.7 # Layer utilization (%)