4,5c4,5
< sim_ticks 19922000 # Number of ticks simulated
< final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19923000 # Number of ticks simulated
> final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 38523 # Simulator instruction rate (inst/s)
< host_op_rate 38518 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 132470471 # Simulator tick rate (ticks/s)
< host_mem_usage 286104 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 93968 # Simulator instruction rate (inst/s)
> host_op_rate 93947 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 323084408 # Simulator tick rate (ticks/s)
> host_mem_usage 291680 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 19782500 # Total gap between requests
---
> system.physmem.totGap 19783500 # Total gap between requests
203,204c203,204
< system.physmem.totQLat 3750750 # Total ticks spent queuing
< system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3746750 # Total ticks spent queuing
> system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 44555.18 # Average gap between requests
---
> system.physmem.avgGap 44557.43 # Average gap between requests
248c248
< system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states
282c282
< system.cpu.numCycles 39845 # number of cpu cycles simulated
---
> system.cpu.numCycles 39847 # number of cpu cycles simulated
313,314c313,314
< system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle
440c440
< system.cpu.iq.rate 0.221860 # Inst issue rate
---
> system.cpu.iq.rate 0.221849 # Inst issue rate
484c484
< system.cpu.iew.exec_rate 0.212950 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.212939 # Inst execution rate
490c490
< system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle
562c562
< system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling
565,568c565,568
< system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads
574c574
< system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use
579c579
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor
604,605c604,605
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles
608,611c608,611
< system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles
628,629c628,629
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency
632,635c632,635
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency
660,661c660,661
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles
664,667c664,667
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles
676,677c676,677
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency
680,683c680,683
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
686c686
< system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use
691c691
< system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor
712,717c712,717
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles
730,735c730,735
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency
756,761c756,761
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles
768,773c768,773
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
776c776
< system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use
781,782c781,782
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor
787,788c787,788
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
816,817c816,817
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles
820c820
< system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles
822,823c822,823
< system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles
825c825
< system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles
852,853c852,853
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency
856c856
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
858,859c858,859
< system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
861c861
< system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency
884,885c884,885
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles
888c888
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles
890,891c890,891
< system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles
893c893
< system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles
908,909c908,909
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency
912c912
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
914,915c914,915
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
917c917
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
918a919,924
> system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
932,933c938,939
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram
935,936c941,942
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram
939c945
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 19922000 # Number of ticks simulated
< final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19923000 # Number of ticks simulated
> final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 38523 # Simulator instruction rate (inst/s)
< host_op_rate 38518 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 132470471 # Simulator tick rate (ticks/s)
< host_mem_usage 286104 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 93968 # Simulator instruction rate (inst/s)
> host_op_rate 93947 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 323084408 # Simulator tick rate (ticks/s)
> host_mem_usage 291680 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 19782500 # Total gap between requests
---
> system.physmem.totGap 19783500 # Total gap between requests
203,204c203,204
< system.physmem.totQLat 3750750 # Total ticks spent queuing
< system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3746750 # Total ticks spent queuing
> system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 44555.18 # Average gap between requests
---
> system.physmem.avgGap 44557.43 # Average gap between requests
248c248
< system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states
282c282
< system.cpu.numCycles 39845 # number of cpu cycles simulated
---
> system.cpu.numCycles 39847 # number of cpu cycles simulated
313,314c313,314
< system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle
440c440
< system.cpu.iq.rate 0.221860 # Inst issue rate
---
> system.cpu.iq.rate 0.221849 # Inst issue rate
484c484
< system.cpu.iew.exec_rate 0.212950 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.212939 # Inst execution rate
490c490
< system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle
562c562
< system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling
565,568c565,568
< system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads
574c574
< system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use
579c579
< system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor
604,605c604,605
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles
608,611c608,611
< system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles
628,629c628,629
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency
632,635c632,635
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency
660,661c660,661
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles
664,667c664,667
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles
676,677c676,677
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency
680,683c680,683
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
686c686
< system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use
691c691
< system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor
712,717c712,717
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles
730,735c730,735
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency
756,761c756,761
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles
768,773c768,773
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
776c776
< system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use
781,782c781,782
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor
787,788c787,788
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
816,817c816,817
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles
820c820
< system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles
822,823c822,823
< system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles
825c825
< system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles
852,853c852,853
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency
856c856
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
858,859c858,859
< system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
861c861
< system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency
884,885c884,885
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles
888c888
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles
890,891c890,891
< system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles
893c893
< system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles
908,909c908,909
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency
912c912
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
914,915c914,915
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
917c917
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
918a919,924
> system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
932,933c938,939
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram
935,936c941,942
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram
939c945
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram