4,5c4,5
< sim_ticks 19079500 # Number of ticks simulated
< final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19030500 # Number of ticks simulated
> final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,9c7,9
< host_inst_rate 82615 # Simulator instruction rate (inst/s)
< host_op_rate 82599 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 272039638 # Simulator tick rate (ticks/s)
---
> host_inst_rate 79159 # Simulator instruction rate (inst/s)
> host_op_rate 79144 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 259986612 # Simulator tick rate (ticks/s)
24,31c24,31
< system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 18951000 # Total gap between requests
---
> system.physmem.totGap 18902000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see
189,203c189,203
< system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation
< system.physmem.totQLat 2851500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation
> system.physmem.totQLat 3599250 # Total ticks spent queuing
> system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM
205,207c205
< system.physmem.totBankLat 6902500 # Total ticks spent accessing banks
< system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst
209,210c207,208
< system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s
212c210
< system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s
215,216c213,214
< system.physmem.busUtil 11.69 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.72 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads
218c216
< system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
224c222
< system.physmem.avgGap 42491.03 # Average gap between requests
---
> system.physmem.avgGap 42381.17 # Average gap between requests
226,227c224,229
< system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1496055976 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1499908042 # Throughput (bytes/s)
238c240
< system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks)
240,241c242,243
< system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.9 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 22.0 # Layer utilization (%)
271c273
< system.cpu.numCycles 38160 # number of cpu cycles simulated
---
> system.cpu.numCycles 38062 # number of cpu cycles simulated
274c276
< system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss
280c282
< system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked
283,285c285,287
< system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total)
287,295c289,297
< system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total)
299,305c301,307
< system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2094 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2089 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking
312,313c314,315
< system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking
---
> system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking
315,316c317,318
< system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking
---
> system.cpu.rename.RunCycles 1980 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking
319c321
< system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full
---
> system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
328c330
< system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer
340,342c342,344
< system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle
344,350c346,352
< system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle
356c358
< system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle
426c428
< system.cpu.iq.rate 0.233255 # Inst issue rate
---
> system.cpu.iq.rate 0.233855 # Inst issue rate
429c431
< system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads
470c472
< system.cpu.iew.exec_rate 0.222746 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.223320 # Inst execution rate
473,474c475,476
< system.cpu.iew.wb_producers 4217 # num instructions producing a value
< system.cpu.iew.wb_consumers 6678 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 4187 # num instructions producing a value
> system.cpu.iew.wb_consumers 6623 # num instructions consuming a value
476,477c478,479
< system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back
482,484c484,486
< system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle
486,494c488,496
< system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle
498c500
< system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle
508a511,545
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
511c548
< system.cpu.rob.rob_reads 21343 # The number of ROB reads
---
> system.cpu.rob.rob_reads 21428 # The number of ROB reads
513,514c550,551
< system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling
518,521c555,558
< system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads
526c563
< system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s)
541c578
< system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks)
543,544c580,581
< system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
546c583
< system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use
551,553c588,590
< system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy
572,577c609,614
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles
590,595c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency
616,621c653,658
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles
628,633c665,670
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
636c673
< system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use
641,643c678,680
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy
645c682
< system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy
672,682c709,719
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles
705,715c742,752
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency
735,745c772,782
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles
757,767c794,804
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
770c807
< system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use
775c812
< system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor
800,807c837,844
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles
824,832c861,869
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
836c873
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked
856,863c893,900
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles
872,879c909,916
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency
< sim_ticks 19079500 # Number of ticks simulated
< final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19030500 # Number of ticks simulated
> final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,9c7,9
< host_inst_rate 82615 # Simulator instruction rate (inst/s)
< host_op_rate 82599 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 272039638 # Simulator tick rate (ticks/s)
---
> host_inst_rate 79159 # Simulator instruction rate (inst/s)
> host_op_rate 79144 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 259986612 # Simulator tick rate (ticks/s)
24,31c24,31
< system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 18951000 # Total gap between requests
---
> system.physmem.totGap 18902000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see
189,203c189,203
< system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation
< system.physmem.totQLat 2851500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation
> system.physmem.totQLat 3599250 # Total ticks spent queuing
> system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM
205,207c205
< system.physmem.totBankLat 6902500 # Total ticks spent accessing banks
< system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst
209,210c207,208
< system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s
212c210
< system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s
215,216c213,214
< system.physmem.busUtil 11.69 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.72 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads
218c216
< system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
224c222
< system.physmem.avgGap 42491.03 # Average gap between requests
---
> system.physmem.avgGap 42381.17 # Average gap between requests
226,227c224,229
< system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1496055976 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1499908042 # Throughput (bytes/s)
238c240
< system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks)
240,241c242,243
< system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.9 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 22.0 # Layer utilization (%)
271c273
< system.cpu.numCycles 38160 # number of cpu cycles simulated
---
> system.cpu.numCycles 38062 # number of cpu cycles simulated
274c276
< system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss
280c282
< system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked
283,285c285,287
< system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total)
287,295c289,297
< system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total)
299,305c301,307
< system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2094 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2089 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking
312,313c314,315
< system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking
---
> system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking
315,316c317,318
< system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking
---
> system.cpu.rename.RunCycles 1980 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking
319c321
< system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full
---
> system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
328c330
< system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer
340,342c342,344
< system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle
344,350c346,352
< system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle
356c358
< system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle
426c428
< system.cpu.iq.rate 0.233255 # Inst issue rate
---
> system.cpu.iq.rate 0.233855 # Inst issue rate
429c431
< system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads
470c472
< system.cpu.iew.exec_rate 0.222746 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.223320 # Inst execution rate
473,474c475,476
< system.cpu.iew.wb_producers 4217 # num instructions producing a value
< system.cpu.iew.wb_consumers 6678 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 4187 # num instructions producing a value
> system.cpu.iew.wb_consumers 6623 # num instructions consuming a value
476,477c478,479
< system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back
482,484c484,486
< system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle
486,494c488,496
< system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle
498c500
< system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle
508a511,545
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
511c548
< system.cpu.rob.rob_reads 21343 # The number of ROB reads
---
> system.cpu.rob.rob_reads 21428 # The number of ROB reads
513,514c550,551
< system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling
518,521c555,558
< system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads
526c563
< system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s)
541c578
< system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks)
543,544c580,581
< system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
546c583
< system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use
551,553c588,590
< system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy
572,577c609,614
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles
590,595c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency
616,621c653,658
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles
628,633c665,670
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
636c673
< system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use
641,643c678,680
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy
645c682
< system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy
672,682c709,719
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles
705,715c742,752
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency
735,745c772,782
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles
757,767c794,804
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
770c807
< system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use
775c812
< system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor
800,807c837,844
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles
824,832c861,869
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
836c873
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked
856,863c893,900
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles
872,879c909,916
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency